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72 lines
2.4 KiB
Plaintext
72 lines
2.4 KiB
Plaintext
;Atart 2600 Program Stub - C02 Assembly Language File
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;Preset Total Number of Kernal Lines
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KNLLNS SET 192 ;192 Lines on NTSC Television
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;Variables Used By Other Libraries
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TEMP0 EQU $E0 ;Temporary Storage
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TEMP1 EQU $E1
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TEMP2 EQU $E2
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TEMP3 EQU $E3
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;Initialization Code
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; From CLEAN_START macro by Andrew Davie
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; Standardised STArt-up code, clears STAck, all TIA registers and RAM to 0
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; Sets STAck pointer to $FF, and all registers to 0
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; Sets decimal mode off, sets interrupt flag (kind of un-necessary)
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; Use as very first section of code on boot (ie: at reset)
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; Code written to minimise total ROM usage - uses weird 6502 knowledge :)
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START: SEI
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CLD
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LDX #0
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TXA
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TAY
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STARTC: DEX
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TXS
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PHA
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BNE STARTC
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JSR SETUP ;Execute Setup Code
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MAIN: LDA #2 ;Vertical Sync On Bit Mask
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LDX #49 ;41 scanlines * 76 cycles / 64
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STA WSYNC ;Wait for SYNC (halts CPU until end of scanline)
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STA VSYNC ;Turn On Vertical Sync
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STX TIM64T ;Set timer to go off in 41 scanlines
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STA WSYNC ;First Scanline of VSYNC
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STA WSYNC ;Second Scanline of VSYNC
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LDA #0 ;Vertical Sync Off Bit Mask
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STA WSYNC ;Third Scanline of VSYNC
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STA VSYNC ;Turn Off Vertical Sync
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JSR VRTBLK ;Execute Vertical Blank Code
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STA WSYNC ;Wait For Horizontal Sync
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STA HMOVE ;Execute Horizontal Moves
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JSR CLRHMX ;Clear Horizontal Move Registers
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WTVBLK: STA WSYNC ;Wait for End of Vertical Blank
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LDA INTIM ;Check Timer
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BNE WTVBLK ;Loop If Not Zero
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STA VBLANK ;Turn off Vertical Blank
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JSR KERNEL ;Execute Kernel Code
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STA WSYNC ;Wait for End of Scanline
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LDA #2 ;Vertical Blank On Bit Mask
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STA VBLANK ;Turn on Vertical Blank
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LDA #32 ;27 scanlines * 76 cycles / 64
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STA TIM64T ;Set Timer for 27 scanlines
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JSR OVRSCN ;Execute Overscan Code
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WTOSCN: STA WSYNC ;Wait for End of Overscan
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LDA INTIM ;Check Time
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BNE WTOSCN ;Loop If Not Zero
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BEQ MAIN ;Loop Back to Vertical Sync
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IRQBRK: RTI ;Catch 6502 Break Instructions
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CLRHMR: NOP ; 2 8 (+6 for calling JSR)
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JSR CLRHMX ;12 20
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LDA #0 ; 2 22 - Clear Horizontal Move Registers
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LDX #4 ; 2 24
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CLRHML STA HMP0,X ; - Safe to Clear 24 Cycles after HMOVE
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DEX
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BPL CLRHML
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CLRHMX: RTS
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