2021-03-18 03:38:55 +00:00
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//
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// ZXSpectrum.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 17/03/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "ZXSpectrum.hpp"
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2021-03-18 16:14:48 +00:00
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#define LOG_PREFIX "[Spectrum] "
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2021-03-18 03:38:55 +00:00
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#include "../../MachineTypes.hpp"
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2021-03-18 14:43:51 +00:00
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#include "../../../Processors/Z80/Z80.hpp"
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2021-03-18 16:14:48 +00:00
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#include "../../../Components/AudioToggle/AudioToggle.hpp"
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#include "../../../Components/AY38910/AY38910.hpp"
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#include "../../../Outputs/Log.hpp"
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#include "../../../Outputs/Speaker/Implementation/CompoundSource.hpp"
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#include "../../../Outputs/Speaker/Implementation/LowpassSpeaker.hpp"
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#include "../../../Outputs/Speaker/Implementation/SampleSource.hpp"
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2021-03-18 14:18:17 +00:00
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#include "../../../Analyser/Static/ZXSpectrum/Target.hpp"
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2021-03-18 03:38:55 +00:00
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2021-03-18 14:18:17 +00:00
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#include <array>
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namespace {
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const unsigned int ClockRate = 3'500'000;
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}
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namespace Sinclair {
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namespace ZXSpectrum {
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using Model = Analyser::Static::ZXSpectrum::Target::Model;
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template<Model model> class ConcreteMachine:
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public Machine,
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2021-03-18 14:18:17 +00:00
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public MachineTypes::ScanProducer,
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public MachineTypes::TimedMachine,
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public CPU::Z80::BusHandler {
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public:
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ConcreteMachine(const Analyser::Static::ZXSpectrum::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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z80_(*this),
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ay_(GI::AY38910::Personality::AY38910, audio_queue_),
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audio_toggle_(audio_queue_),
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mixer_(ay_, audio_toggle_),
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speaker_(mixer_)
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{
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set_clock_rate(ClockRate);
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2021-03-18 16:23:54 +00:00
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speaker_.set_input_rate(float(ClockRate) / 2.0f);
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2021-03-18 14:18:17 +00:00
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// With only the +2a and +3 currently supported, the +3 ROM is always
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// the one required.
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const auto roms =
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rom_fetcher({ {"ZXSpectrum", "the +2a/+3 ROM", "plus3.rom", 64 * 1024, 0x96e3c17a} });
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if(!roms[0]) throw ROMMachine::Error::MissingROMs;
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memcpy(rom_.data(), roms[0]->data(), std::min(rom_.size(), roms[0]->size()));
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2021-03-18 14:43:51 +00:00
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// Set up initial memory map.
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update_memory_map();
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// TODO: insert media.
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(void)target;
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}
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2021-03-18 16:23:54 +00:00
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~ConcreteMachine() {
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audio_queue_.flush();
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}
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2021-03-18 14:18:17 +00:00
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// MARK: - TimedMachine
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void run_for(const Cycles cycles) override {
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z80_.run_for(cycles);
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}
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2021-03-18 16:23:54 +00:00
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void flush() {
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update_audio();
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audio_queue_.perform();
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}
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2021-03-18 14:18:17 +00:00
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// MARK: - ScanProducer
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void set_scan_target(Outputs::Display::ScanTarget *scan_target) final {
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(void)scan_target;
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}
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Outputs::Display::ScanStatus get_scaled_scan_status() const final {
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// TODO.
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return Outputs::Display::ScanStatus();
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}
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2021-03-18 14:43:51 +00:00
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// MARK: - BusHandler
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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time_since_audio_update_ += cycle.length;
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2021-03-18 16:14:48 +00:00
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// Ignore all but terminal cycles.
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// TODO: I doubt this is correct for timing.
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if(!cycle.is_terminal()) return HalfCycles(0);
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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using PartialMachineCycle = CPU::Z80::PartialMachineCycle;
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switch(cycle.operation) {
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default: break;
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case PartialMachineCycle::ReadOpcode:
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case PartialMachineCycle::Read:
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*cycle.value = read_pointers_[address >> 14][address];
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break;
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case PartialMachineCycle::Write:
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write_pointers_[address >> 14][address] = *cycle.value;
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break;
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case PartialMachineCycle::Output:
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if(!(address&1)) {
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// TODO: rest of port FE.
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update_audio();
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audio_toggle_.set_output(*cycle.value & 0x10);
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}
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switch(address) {
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default: break;
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case 0x1ffd:
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// Write to +2a/+3 paging register.
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port1ffd_ = *cycle.value;
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update_memory_map();
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break;
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case 0x7ffd:
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// Write to classic 128kb paging register.
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disable_paging_ |= *cycle.value & 0x20;
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port7ffd_ = *cycle.value;
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update_memory_map();
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break;
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case 0xfffd:
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// Select AY register.
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update_audio();
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ay_.set_control_lines(GI::AY38910::ControlLines(GI::AY38910::BDIR | GI::AY38910::BC2 | GI::AY38910::BC1));
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ay_.set_data_input(*cycle.value);
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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break;
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case 0xbffd:
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// Write to AY register.
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update_audio();
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ay_.set_control_lines(GI::AY38910::ControlLines(GI::AY38910::BDIR | GI::AY38910::BC2));
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ay_.set_data_input(*cycle.value);
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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break;
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}
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break;
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case PartialMachineCycle::Input:
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if(!(address&1)) {
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// TODO: port FE.
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}
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switch(address) {
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default: break;
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case 0xfffd:
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// Read from AY register.
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update_audio();
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ay_.set_control_lines(GI::AY38910::ControlLines(GI::AY38910::BC2 | GI::AY38910::BC1));
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*cycle.value &= ay_.get_data_output();
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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break;
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}
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break;
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}
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2021-03-18 14:43:51 +00:00
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return HalfCycles(0);
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}
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2021-03-18 14:18:17 +00:00
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private:
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CPU::Z80::Processor<ConcreteMachine, false, false> z80_;
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// MARK: - Memory.
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std::array<uint8_t, 64*1024> rom_;
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std::array<uint8_t, 128*1024> ram_;
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std::array<uint8_t, 16*1024> scratch_;
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const uint8_t *read_pointers_[4];
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uint8_t *write_pointers_[4];
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uint8_t port1ffd_ = 0;
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uint8_t port7ffd_ = 0;
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bool disable_paging_ = false;
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void update_memory_map() {
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// If paging is permanently disabled, don't react.
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if(disable_paging_) {
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return;
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}
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if(port1ffd_ & 1) {
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// "Special paging mode", i.e. one of four fixed
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// RAM configurations, port 7ffd doesn't matter.
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switch(port1ffd_ & 0x6) {
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default:
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case 0x00:
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set_memory(0, &ram_[0 * 16384], &ram_[0 * 16384]);
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set_memory(1, &ram_[1 * 16384], &ram_[1 * 16384]);
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set_memory(2, &ram_[2 * 16384], &ram_[2 * 16384]);
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set_memory(3, &ram_[3 * 16384], &ram_[3 * 16384]);
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break;
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case 0x02:
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set_memory(0, &ram_[4 * 16384], &ram_[4 * 16384]);
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set_memory(1, &ram_[5 * 16384], &ram_[5 * 16384]);
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set_memory(2, &ram_[6 * 16384], &ram_[6 * 16384]);
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set_memory(3, &ram_[7 * 16384], &ram_[7 * 16384]);
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break;
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case 0x04:
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set_memory(0, &ram_[4 * 16384], &ram_[4 * 16384]);
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set_memory(1, &ram_[5 * 16384], &ram_[5 * 16384]);
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set_memory(2, &ram_[6 * 16384], &ram_[6 * 16384]);
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set_memory(3, &ram_[3 * 16384], &ram_[3 * 16384]);
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break;
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case 0x06:
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set_memory(0, &ram_[4 * 16384], &ram_[4 * 16384]);
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set_memory(1, &ram_[7 * 16384], &ram_[7 * 16384]);
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set_memory(2, &ram_[6 * 16384], &ram_[6 * 16384]);
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set_memory(3, &ram_[3 * 16384], &ram_[3 * 16384]);
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break;
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}
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return;
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}
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// Apply standard 128kb-esque mapping (albeit with extra ROM to pick from).
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const auto rom = &rom_[ (((port1ffd_ >> 1) & 2) | ((port7ffd_ >> 4) & 1)) * 16384];
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set_memory(0, rom, nullptr);
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set_memory(1, &ram_[5 * 16384], &ram_[5 * 16384]);
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set_memory(2, &ram_[2 * 16384], &ram_[2 * 16384]);
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const auto high_ram = &ram_[(port7ffd_ & 7) * 16384];
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set_memory(3, high_ram, high_ram);
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}
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void set_memory(int bank, const uint8_t *read, uint8_t *write) {
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read_pointers_[bank] = read - bank*16384;
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write_pointers_[bank] = (write ? write : scratch_.data()) - bank*16384;
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}
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2021-03-18 16:14:48 +00:00
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// MARK: - Audio.
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Concurrency::DeferringAsyncTaskQueue audio_queue_;
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GI::AY38910::AY38910<false> ay_;
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Audio::Toggle audio_toggle_;
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Outputs::Speaker::CompoundSource<GI::AY38910::AY38910<false>, Audio::Toggle> mixer_;
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Outputs::Speaker::LowpassSpeaker<Outputs::Speaker::CompoundSource<GI::AY38910::AY38910<false>, Audio::Toggle>> speaker_;
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HalfCycles time_since_audio_update_;
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void update_audio() {
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speaker_.run_for(audio_queue_, time_since_audio_update_.divide_cycles(Cycles(2)));
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}
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2021-03-18 14:18:17 +00:00
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};
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}
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}
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2021-03-18 03:38:55 +00:00
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using namespace Sinclair::ZXSpectrum;
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Machine *Machine::ZXSpectrum(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
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const auto zx_target = dynamic_cast<const Analyser::Static::ZXSpectrum::Target *>(target);
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switch(zx_target->model) {
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case Model::Plus2a: return new ConcreteMachine<Model::Plus2a>(*zx_target, rom_fetcher);
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case Model::Plus3: return new ConcreteMachine<Model::Plus3>(*zx_target, rom_fetcher);
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}
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2021-03-18 03:38:55 +00:00
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return nullptr;
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}
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Machine::~Machine() {}
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