2019-06-08 22:47:11 +00:00
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//
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// z8530.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 07/06/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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2024-01-17 04:34:46 +00:00
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#pragma once
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2019-06-08 22:47:11 +00:00
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#include <cstdint>
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2023-05-10 21:02:18 +00:00
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namespace Zilog::SCC {
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2019-06-08 22:47:11 +00:00
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/*!
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Models the Zilog 8530 SCC, a serial adaptor.
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*/
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class z8530 {
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2024-11-30 03:43:54 +00:00
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public:
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/*
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**Interface for emulated machine.**
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2019-06-12 21:51:50 +00:00
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2024-11-30 03:43:54 +00:00
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Notes on addressing below:
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2019-06-08 22:47:11 +00:00
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2024-11-30 03:43:54 +00:00
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There's no inherent ordering of the two 'address' lines,
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A/B and C/D, but the methods below assume:
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2019-06-08 22:47:11 +00:00
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2024-11-30 03:43:54 +00:00
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A/B = A0
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C/D = A1
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*/
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2019-09-30 02:08:16 +00:00
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2024-11-30 03:43:54 +00:00
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/// Performs a read from the SCC; see above for conventions as to 'address'.
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std::uint8_t read(int address);
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/// Performs a write to the SCC; see above for conventions as to 'address'.
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void write(int address, std::uint8_t value);
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/// Resets the SCC.
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void reset();
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2019-06-12 21:51:50 +00:00
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2024-11-30 03:43:54 +00:00
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/// @returns The current value of the status output: @c true for active; @c false for inactive.
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bool get_interrupt_line() const;
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2019-09-30 02:08:16 +00:00
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2024-11-30 03:43:54 +00:00
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struct Delegate {
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/*!
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Communicates that @c scc now has the interrupt line status @c new_status.
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*/
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virtual void did_change_interrupt_status(z8530 *, bool new_status) = 0;
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};
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/*!
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Sets the delegate for this SCC. If this is a new delegate it is sent
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an immediate did_change_interrupt_status message, to get it
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up to speed.
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*/
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void set_delegate(Delegate *const delegate) {
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if(delegate_ == delegate) return;
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delegate_ = delegate;
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delegate_->did_change_interrupt_status(this, get_interrupt_line());
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}
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/*
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**Interface for serial port input.**
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*/
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void set_dcd(int port, bool level);
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2019-06-08 22:47:11 +00:00
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2024-11-30 03:43:54 +00:00
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private:
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class Channel {
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public:
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uint8_t read(bool data, uint8_t pointer);
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void write(bool data, uint8_t pointer, uint8_t value);
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void set_dcd(bool level);
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bool get_interrupt_line() const;
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private:
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uint8_t data_ = 0xff;
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2024-11-30 03:43:54 +00:00
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enum class Parity {
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Even, Odd, Off
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} parity_ = Parity::Off;
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2024-11-30 03:43:54 +00:00
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enum class StopBits {
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Synchronous, OneBit, OneAndAHalfBits, TwoBits
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} stop_bits_ = StopBits::Synchronous;
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2019-06-12 21:51:50 +00:00
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2024-11-30 03:43:54 +00:00
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enum class Sync {
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Monosync, Bisync, SDLC, External
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} sync_mode_ = Sync::Monosync;
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2019-06-12 21:51:50 +00:00
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2024-11-30 03:43:54 +00:00
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int clock_rate_multiplier_ = 1;
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2019-06-12 21:51:50 +00:00
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2024-11-30 03:43:54 +00:00
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uint8_t interrupt_mask_ = 0; // i.e. Write Register 0x1.
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2019-06-13 02:19:25 +00:00
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2024-11-30 03:43:54 +00:00
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uint8_t external_interrupt_mask_ = 0; // i.e. Write Register 0xf.
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bool external_status_interrupt_ = false;
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uint8_t external_interrupt_status_ = 0;
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2019-06-12 21:51:50 +00:00
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2024-11-30 03:43:54 +00:00
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bool dcd_ = false;
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} channels_[2];
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2019-06-13 02:19:25 +00:00
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2024-11-30 03:43:54 +00:00
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uint8_t pointer_ = 0;
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2019-06-13 02:19:25 +00:00
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2024-11-30 03:43:54 +00:00
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uint8_t interrupt_vector_ = 0;
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2019-06-13 02:19:25 +00:00
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2024-11-30 03:43:54 +00:00
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uint8_t master_interrupt_control_ = 0;
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2019-07-24 03:13:03 +00:00
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2024-11-30 03:43:54 +00:00
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bool previous_interrupt_line_ = false;
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void update_delegate();
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Delegate *delegate_ = nullptr;
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2019-06-08 22:47:11 +00:00
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};
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}
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