2015-07-16 23:56:02 +00:00
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//
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2017-05-15 02:08:15 +00:00
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// 6502AllRAM.hpp
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2015-07-26 19:25:11 +00:00
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// CLK
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2015-07-16 23:56:02 +00:00
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//
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// Created by Thomas Harte on 13/07/2015.
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2018-05-13 19:19:52 +00:00
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// Copyright 2015 Thomas Harte. All rights reserved.
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2015-07-16 23:56:02 +00:00
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//
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2017-05-15 02:08:15 +00:00
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#ifndef MOS6502AllRAM_cpp
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#define MOS6502AllRAM_cpp
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2015-07-16 23:56:02 +00:00
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2020-10-06 02:23:33 +00:00
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#include "../../6502Esque/6502Selector.hpp"
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2017-09-01 02:10:27 +00:00
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#include "../../AllRAMProcessor.hpp"
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2015-07-16 23:56:02 +00:00
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2023-05-10 21:02:18 +00:00
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namespace CPU::MOS6502 {
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2015-07-16 23:56:02 +00:00
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2017-05-17 01:28:17 +00:00
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class AllRAMProcessor:
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2017-06-04 01:22:16 +00:00
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public ::CPU::AllRAMProcessor {
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2015-07-16 23:56:02 +00:00
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public:
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2021-07-31 01:21:16 +00:00
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static AllRAMProcessor *Processor(CPU::MOS6502Esque::Type type, bool has_cias = false);
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2017-06-04 01:54:42 +00:00
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virtual ~AllRAMProcessor() {}
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2017-06-04 01:22:16 +00:00
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2017-07-28 02:05:29 +00:00
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virtual void run_for(const Cycles cycles) = 0;
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2020-11-03 02:09:32 +00:00
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virtual void run_for_instructions(int) = 0;
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2017-06-04 01:22:16 +00:00
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virtual bool is_jammed() = 0;
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virtual void set_irq_line(bool value) = 0;
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virtual void set_nmi_line(bool value) = 0;
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virtual uint16_t get_value_of_register(Register r) = 0;
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virtual void set_value_of_register(Register r, uint16_t value) = 0;
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2021-07-31 01:21:16 +00:00
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2017-06-04 01:22:16 +00:00
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protected:
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2020-10-12 01:18:01 +00:00
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AllRAMProcessor(size_t memory_size) : ::CPU::AllRAMProcessor(memory_size) {}
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2015-07-16 23:56:02 +00:00
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};
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}
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2017-05-15 02:08:15 +00:00
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#endif /* MOS6502AllRAM_cpp */
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