2017-09-04 18:26:04 +00:00
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//
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// Implementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 04/09/2017.
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2018-05-13 19:19:52 +00:00
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// Copyright 2017 Thomas Harte. All rights reserved.
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2017-09-04 18:26:04 +00:00
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//
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2019-03-02 23:07:05 +00:00
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#include "../../../Outputs/Log.hpp"
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namespace MOS {
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namespace MOS6522 {
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2019-05-08 16:48:29 +00:00
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template <typename T> void MOS6522<T>::access(int address) {
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switch(address) {
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case 0x0:
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// In both handshake and pulse modes, CB2 goes low on any read or write of Port B.
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if(handshake_modes_[1] != HandshakeMode::None) {
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bus_handler_.set_control_line_output(Port::B, Line::Two, false);
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}
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break;
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case 0xf:
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case 0x1:
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// In both handshake and pulse modes, CA2 goes low on any read or write of Port A.
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if(handshake_modes_[0] != HandshakeMode::None) {
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bus_handler_.set_control_line_output(Port::A, Line::Two, false);
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}
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break;
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}
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}
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2017-09-04 18:26:04 +00:00
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template <typename T> void MOS6522<T>::set_register(int address, uint8_t value) {
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address &= 0xf;
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2019-05-08 16:48:29 +00:00
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access(address);
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2017-09-04 18:26:04 +00:00
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switch(address) {
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2019-05-08 16:35:17 +00:00
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case 0x0: // Write Port B.
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2019-05-08 16:48:29 +00:00
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// Store locally and communicate outwards.
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2017-09-04 18:26:04 +00:00
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registers_.output[1] = value;
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2019-05-08 16:35:17 +00:00
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bus_handler_.set_port_output(Port::B, value, registers_.data_direction[1]);
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2017-09-04 18:26:04 +00:00
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registers_.interrupt_flags &= ~(InterruptFlag::CB1ActiveEdge | ((registers_.peripheral_control&0x20) ? 0 : InterruptFlag::CB2ActiveEdge));
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reevaluate_interrupts();
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break;
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case 0xf:
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2019-05-08 16:35:17 +00:00
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case 0x1: // Write Port A.
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2017-09-04 18:26:04 +00:00
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registers_.output[0] = value;
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2019-05-08 16:35:17 +00:00
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bus_handler_.set_port_output(Port::A, value, registers_.data_direction[0]);
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if(handshake_modes_[1] != HandshakeMode::None) {
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bus_handler_.set_control_line_output(Port::A, Line::Two, false);
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}
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2017-09-04 18:26:04 +00:00
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registers_.interrupt_flags &= ~(InterruptFlag::CA1ActiveEdge | ((registers_.peripheral_control&0x02) ? 0 : InterruptFlag::CB2ActiveEdge));
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reevaluate_interrupts();
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break;
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2019-05-08 16:35:17 +00:00
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case 0x2: // Port B direction.
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2017-09-04 18:26:04 +00:00
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registers_.data_direction[1] = value;
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break;
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2019-05-08 16:35:17 +00:00
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case 0x3: // Port A direction.
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2017-09-04 18:26:04 +00:00
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registers_.data_direction[0] = value;
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break;
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// Timer 1
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case 0x6: case 0x4: registers_.timer_latch[0] = (registers_.timer_latch[0]&0xff00) | value; break;
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case 0x5: case 0x7:
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2017-10-04 02:04:15 +00:00
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registers_.timer_latch[0] = (registers_.timer_latch[0]&0x00ff) | static_cast<uint16_t>(value << 8);
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2017-09-04 18:26:04 +00:00
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registers_.interrupt_flags &= ~InterruptFlag::Timer1;
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if(address == 0x05) {
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registers_.next_timer[0] = registers_.timer_latch[0];
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timer_is_running_[0] = true;
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}
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reevaluate_interrupts();
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break;
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// Timer 2
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case 0x8: registers_.timer_latch[1] = value; break;
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case 0x9:
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registers_.interrupt_flags &= ~InterruptFlag::Timer2;
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2017-10-04 02:04:15 +00:00
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registers_.next_timer[1] = registers_.timer_latch[1] | static_cast<uint16_t>(value << 8);
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2017-09-04 18:26:04 +00:00
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timer_is_running_[1] = true;
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reevaluate_interrupts();
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break;
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// Shift
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case 0xa: registers_.shift = value; break;
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// Control
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case 0xb:
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registers_.auxiliary_control = value;
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break;
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2019-05-08 16:48:29 +00:00
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case 0xc: {
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2017-09-04 18:26:04 +00:00
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registers_.peripheral_control = value;
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2019-05-08 16:48:29 +00:00
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for(int port = 0; port < 2; ++port) {
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handshake_modes_[port] = HandshakeMode::None;
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switch(value & 0x0e) {
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default: break;
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2019-05-08 16:35:17 +00:00
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2019-05-08 16:48:29 +00:00
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case 0x00: // Negative interrupt input; set CA2 interrupt on negative CA2 transition, clear on access to Port A register.
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case 0x02: // Independent negative interrupt input; set CA2 interrupt on negative transition, don't clear automatically.
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case 0x04: // Positive interrupt input; set CA2 interrupt on positive CA2 transition, clear on access to Port A register.
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case 0x06: // Independent positive interrupt input; set CA2 interrupt on positive transition, don't clear automatically.
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break;
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2019-05-08 16:35:17 +00:00
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2019-05-08 16:48:29 +00:00
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case 0x08: // Handshake: set CA2 to low on any read or write of Port A; set to high on an active transition of CA1.
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handshake_modes_[port] = HandshakeMode::Handshake;
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break;
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2019-05-08 16:35:17 +00:00
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2019-05-08 16:48:29 +00:00
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case 0x0a: // Pulse output: CA2 is low for one cycle following a read or write of Port A.
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handshake_modes_[port] = HandshakeMode::Pulse;
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break;
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2019-05-08 16:35:17 +00:00
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2019-05-08 16:48:29 +00:00
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case 0x0c: // Manual output: CA2 low.
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bus_handler_.set_control_line_output(Port(port), Line::Two, false);
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break;
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2019-05-08 16:35:17 +00:00
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2019-05-08 16:48:29 +00:00
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case 0x0e: // Manual output: CA2 high.
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bus_handler_.set_control_line_output(Port(port), Line::Two, true);
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break;
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}
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value >>= 4;
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2017-09-04 18:26:04 +00:00
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}
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2019-05-08 16:48:29 +00:00
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} break;
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2017-09-04 18:26:04 +00:00
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// Interrupt control
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case 0xd:
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registers_.interrupt_flags &= ~value;
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reevaluate_interrupts();
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break;
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case 0xe:
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if(value&0x80)
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registers_.interrupt_enable |= value;
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else
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registers_.interrupt_enable &= ~value;
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reevaluate_interrupts();
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break;
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}
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}
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template <typename T> uint8_t MOS6522<T>::get_register(int address) {
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address &= 0xf;
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2019-05-08 16:48:29 +00:00
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access(address);
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2017-09-04 18:26:04 +00:00
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switch(address) {
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case 0x0:
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registers_.interrupt_flags &= ~(InterruptFlag::CB1ActiveEdge | InterruptFlag::CB2ActiveEdge);
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reevaluate_interrupts();
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return get_port_input(Port::B, registers_.data_direction[1], registers_.output[1]);
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case 0xf: // TODO: handshake, latching
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case 0x1:
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registers_.interrupt_flags &= ~(InterruptFlag::CA1ActiveEdge | InterruptFlag::CA2ActiveEdge);
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reevaluate_interrupts();
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return get_port_input(Port::A, registers_.data_direction[0], registers_.output[0]);
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case 0x2: return registers_.data_direction[1];
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case 0x3: return registers_.data_direction[0];
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// Timer 1
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case 0x4:
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registers_.interrupt_flags &= ~InterruptFlag::Timer1;
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reevaluate_interrupts();
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return registers_.timer[0] & 0x00ff;
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case 0x5: return registers_.timer[0] >> 8;
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case 0x6: return registers_.timer_latch[0] & 0x00ff;
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case 0x7: return registers_.timer_latch[0] >> 8;
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// Timer 2
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case 0x8:
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registers_.interrupt_flags &= ~InterruptFlag::Timer2;
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reevaluate_interrupts();
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return registers_.timer[1] & 0x00ff;
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case 0x9: return registers_.timer[1] >> 8;
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case 0xa: return registers_.shift;
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case 0xb: return registers_.auxiliary_control;
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case 0xc: return registers_.peripheral_control;
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case 0xd: return registers_.interrupt_flags | (get_interrupt_line() ? 0x80 : 0x00);
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case 0xe: return registers_.interrupt_enable | 0x80;
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}
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return 0xff;
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}
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template <typename T> uint8_t MOS6522<T>::get_port_input(Port port, uint8_t output_mask, uint8_t output) {
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uint8_t input = bus_handler_.get_port_input(port);
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return (input & ~output_mask) | (output & output_mask);
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}
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2018-05-12 02:24:33 +00:00
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template <typename T> T &MOS6522<T>::bus_handler() {
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return bus_handler_;
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}
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2017-09-04 18:26:04 +00:00
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// Delegate and communications
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template <typename T> void MOS6522<T>::reevaluate_interrupts() {
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bool new_interrupt_status = get_interrupt_line();
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if(new_interrupt_status != last_posted_interrupt_status_) {
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last_posted_interrupt_status_ = new_interrupt_status;
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bus_handler_.set_interrupt_status(new_interrupt_status);
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}
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}
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2019-03-02 23:07:05 +00:00
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2019-05-08 16:35:17 +00:00
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template <typename T> void MOS6522<T>::set_control_line_input(Port port, Line line, bool value) {
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switch(line) {
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case Line::One:
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if( value != control_inputs_[port].line_one &&
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value == !!(registers_.peripheral_control & (port ? 0x10 : 0x01))
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) {
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2019-05-08 16:48:29 +00:00
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// In handshake mode, any transition on C[A/B]1 sets output high on C[A/B]2.
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2019-05-08 16:35:17 +00:00
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if(handshake_modes_[port] == HandshakeMode::Handshake) {
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2019-05-08 16:48:29 +00:00
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bus_handler_.set_control_line_output(port, Line::Two, true);
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2019-05-08 16:35:17 +00:00
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}
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registers_.interrupt_flags |= port ? InterruptFlag::CB1ActiveEdge : InterruptFlag::CA1ActiveEdge;
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reevaluate_interrupts();
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}
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control_inputs_[port].line_one = value;
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break;
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case Line::Two:
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// TODO: output modes, but probably elsewhere?
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if( value != control_inputs_[port].line_two && // i.e. value has changed ...
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!(registers_.peripheral_control & (port ? 0x80 : 0x08)) && // ... and line is input ...
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value == !!(registers_.peripheral_control & (port ? 0x40 : 0x04)) // ... and it's either high or low, as required
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) {
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registers_.interrupt_flags |= port ? InterruptFlag::CB2ActiveEdge : InterruptFlag::CA2ActiveEdge;
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reevaluate_interrupts();
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}
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control_inputs_[port].line_two = value;
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break;
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}
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}
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template <typename T> void MOS6522<T>::do_phase2() {
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registers_.last_timer[0] = registers_.timer[0];
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registers_.last_timer[1] = registers_.timer[1];
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if(registers_.timer_needs_reload) {
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registers_.timer_needs_reload = false;
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registers_.timer[0] = registers_.timer_latch[0];
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} else {
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registers_.timer[0] --;
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}
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registers_.timer[1] --;
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if(registers_.next_timer[0] >= 0) {
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registers_.timer[0] = static_cast<uint16_t>(registers_.next_timer[0]);
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registers_.next_timer[0] = -1;
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}
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if(registers_.next_timer[1] >= 0) {
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registers_.timer[1] = static_cast<uint16_t>(registers_.next_timer[1]);
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registers_.next_timer[1] = -1;
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}
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2019-05-08 16:48:29 +00:00
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// In pulse modes, CA2 and CB2 go high again on the next clock edge.
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if(handshake_modes_[1] == HandshakeMode::Pulse) {
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bus_handler_.set_control_line_output(Port::B, Line::Two, true);
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}
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if(handshake_modes_[0] == HandshakeMode::Pulse) {
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bus_handler_.set_control_line_output(Port::A, Line::Two, true);
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}
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2019-05-08 16:35:17 +00:00
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}
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template <typename T> void MOS6522<T>::do_phase1() {
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// IRQ is raised on the half cycle after overflow
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if((registers_.timer[1] == 0xffff) && !registers_.last_timer[1] && timer_is_running_[1]) {
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timer_is_running_[1] = false;
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registers_.interrupt_flags |= InterruptFlag::Timer2;
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reevaluate_interrupts();
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}
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if((registers_.timer[0] == 0xffff) && !registers_.last_timer[0] && timer_is_running_[0]) {
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registers_.interrupt_flags |= InterruptFlag::Timer1;
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reevaluate_interrupts();
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if(registers_.auxiliary_control&0x40)
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registers_.timer_needs_reload = true;
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else
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timer_is_running_[0] = false;
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}
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}
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/*! Runs for a specified number of half cycles. */
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template <typename T> void MOS6522<T>::run_for(const HalfCycles half_cycles) {
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int number_of_half_cycles = half_cycles.as_int();
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if(is_phase2_) {
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do_phase2();
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number_of_half_cycles--;
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}
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while(number_of_half_cycles >= 2) {
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do_phase1();
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do_phase2();
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number_of_half_cycles -= 2;
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}
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if(number_of_half_cycles) {
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do_phase1();
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is_phase2_ = true;
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} else {
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is_phase2_ = false;
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}
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}
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/*! Runs for a specified number of cycles. */
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template <typename T> void MOS6522<T>::run_for(const Cycles cycles) {
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int number_of_cycles = cycles.as_int();
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while(number_of_cycles--) {
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do_phase1();
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do_phase2();
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}
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}
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/*! @returns @c true if the IRQ line is currently active; @c false otherwise. */
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template <typename T> bool MOS6522<T>::get_interrupt_line() {
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uint8_t interrupt_status = registers_.interrupt_flags & registers_.interrupt_enable & 0x7f;
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return !!interrupt_status;
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}
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2019-03-02 23:07:05 +00:00
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}
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}
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