2021-04-08 01:57:40 +00:00
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//
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// Z80ContentionTests.cpp
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// Clock SignalTests
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//
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// Created by Thomas Harte on 7/4/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include "../../../Processors/Z80/Z80.hpp"
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namespace {
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static constexpr uint16_t initial_pc = 0;
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struct CapturingZ80: public CPU::Z80::BusHandler {
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CapturingZ80(const std::initializer_list<uint8_t> &code) : z80_(*this) {
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// Take a copy of the code.
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std::copy(code.begin(), code.end(), ram_);
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// Skip the three cycles the Z80 spends on a reset, and
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// purge them from the record.
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run_for(3);
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bus_records_.clear();
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// Set the refresh address to the EE page.
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z80_.set_value_of_register(CPU::Z80::Register::I, 0xe0);
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}
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void run_for(int cycles) {
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z80_.run_for(HalfCycles(Cycles(cycles)));
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}
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/// A record of the state of the address bus, MREQ, IOREQ and RFSH lines,
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/// upon every clock transition.
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struct BusRecord {
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uint16_t address = 0xffff;
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bool mreq = false, ioreq = false, refresh = false;
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};
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HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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// Log the activity.
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const uint8_t* const bus_state = cycle.bus_state();
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for(int c = 0; c < cycle.length.as<int>(); c++) {
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bus_records_.emplace_back();
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// TODO: I think everything tested here should have an address,
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// but am currently unsure whether the reset program puts the
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// address bus in high impedance, as bus req/ack does.
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if(cycle.address) {
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bus_records_.back().address = *cycle.address;
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}
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bus_records_.back().mreq = bus_state[c] & CPU::Z80::PartialMachineCycle::Line::MREQ;
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bus_records_.back().ioreq = bus_state[c] & CPU::Z80::PartialMachineCycle::Line::IOREQ;
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bus_records_.back().refresh = bus_state[c] & CPU::Z80::PartialMachineCycle::Line::RFSH;
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}
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// Provide only reads.
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if(
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cycle.operation == CPU::Z80::PartialMachineCycle::Read ||
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cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode
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) {
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*cycle.value = ram_[*cycle.address];
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}
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return HalfCycles(0);
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}
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const std::vector<BusRecord> &bus_records() const {
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return bus_records_;
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}
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std::vector<BusRecord> cycle_records() const {
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std::vector<BusRecord> cycle_records;
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for(size_t c = 0; c < bus_records_.size(); c += 2) {
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cycle_records.push_back(bus_records_[c]);
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}
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return cycle_records;
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}
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private:
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CPU::Z80::Processor<CapturingZ80, false, false> z80_;
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uint8_t ram_[65536];
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std::vector<BusRecord> bus_records_;
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};
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}
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@interface Z80ContentionTests : XCTestCase
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@end
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/*!
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Tests the Z80's MREQ, IOREQ and address outputs for correlation to those
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observed by ZX Spectrum users in the software-side documentation of
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contended memory timings.
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*/
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@implementation Z80ContentionTests {
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}
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struct ContentionCheck {
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uint16_t address;
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int length;
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};
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/*!
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Checks that the accumulated bus activity in @c z80 matches the expectations given in @c contentions if
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processed by a Sinclair 48k or 128k ULA.
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*/
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- (void)validate48Contention:(const std::initializer_list<ContentionCheck> &)contentions z80:(const CapturingZ80 &)z80 {
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// 48[/128]k contention logic: triggered on address alone, _unless_
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// MREQ is also active.
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//
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// I think the source I'm using also implicitly assumes that refresh
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// addresses are outside of the contended area, and doesn't check them.
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// So unlike the actual ULA I'm also ignoring any address while refresh
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// is asserted.
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int count = -1;
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uint16_t address = 0;
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auto contention = contentions.begin();
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const auto bus_records = z80.cycle_records();
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for(const auto &record: bus_records) {
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++count;
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if(
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!count || // i.e. is at start.
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(&record == &bus_records.back()) || // i.e. is at end.
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2021-04-08 23:21:35 +00:00
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!record.mreq // i.e. beginning of a new contention.
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2021-04-08 01:57:40 +00:00
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) {
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if(count) {
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XCTAssertNotEqual(contention, contentions.end());
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XCTAssertEqual(contention->address, address);
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XCTAssertEqual(contention->length, count);
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++contention;
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}
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count = 1;
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address = record.address;
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}
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}
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XCTAssertEqual(contention, contentions.end());
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}
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/*!
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Checks that the accumulated bus activity in @c z80 matches the expectations given in @c contentions if
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processed by an Amstrad gate array.
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*/
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- (void)validatePlus3Contention:(const std::initializer_list<ContentionCheck> &)contentions z80:(const CapturingZ80 &)z80 {
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// +3 contention logic: triggered by the leading edge of MREQ, sans refresh.
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int count = -1;
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uint16_t address = 0;
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auto contention = contentions.begin();
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const auto bus_records = z80.bus_records();
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for(size_t c = 0; c < bus_records.size(); c += 2) {
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const bool is_leading_edge = !bus_records[c].mreq && bus_records[c+1].mreq && !bus_records[c].refresh;
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++count;
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if(
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!count || // i.e. is at start.
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(c == bus_records.size() - 2) || // i.e. is at end.
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is_leading_edge // i.e. beginning of a new contention.
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) {
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if(count) {
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XCTAssertNotEqual(contention, contentions.end());
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XCTAssertEqual(contention->address, address);
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XCTAssertEqual(contention->length, count);
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++contention;
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}
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count = 1;
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address = bus_records[c].address;
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}
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}
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XCTAssertEqual(contention, contentions.end());
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}
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// MARK: - Opcode tests.
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2021-04-08 02:07:52 +00:00
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- (void)testSimpleSingleBytes {
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for(uint8_t opcode : {
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0x00, // NOP
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// LD r, r'.
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0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x47,
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0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4f,
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0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x57,
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0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f,
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0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
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0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6f,
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// ALO a, r
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0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x87,
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0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8f,
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0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x97,
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0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9f,
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0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa7,
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0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xaf,
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0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb7,
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0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbf,
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// INC/DEC r
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0x04, 0x05, 0x0c, 0x0d,
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0x14, 0x15, 0x1c, 0x1d,
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0x24, 0x25, 0x2c, 0x2d,
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0xd9, // EXX
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0x08, // EX AF, AF'
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0xeb, // EX DE, HL
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0x27, // DAA
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0x2f, // CPL
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0x3f, // CCF
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0x37, // SCF
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0xf3, // DI
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0xfb, // EI
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0x17, // RLA
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0x1f, // RRA
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0x07, // RLCA
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0x0f, // RRCA
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0xe9, // JP (HL)
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}) {
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CapturingZ80 z80({opcode});
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z80.run_for(4);
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[self validate48Contention:{{initial_pc, 4}} z80:z80];
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[self validatePlus3Contention:{{initial_pc, 4}} z80:z80];
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}
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2021-04-08 01:57:40 +00:00
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}
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@end
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