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CLK/InstructionSets/x86/Decoder.cpp

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Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
//
// x86.cpp
// Clock Signal
//
Switches all American-style dates. I'd failed to configure my new computer appropriately, it seems.
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// Created by Thomas Harte on 01/01/21.
Does the easier part of the easier half of 8086 decoding.
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// Copyright © 2021 Thomas Harte. All rights reserved.
//
Better plans project layout.
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#include "Decoder.hpp"
Does the easier part of the easier half of 8086 decoding.
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Proceeds to three instructions correctly decoded. 'Wow'.
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#include <algorithm>
Muddles drunkenly towards decoding ModRM.
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#include <cassert>
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
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#include <utility>
Muddles drunkenly towards decoding ModRM.
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Adds files for the M50740 and corrects namespace errors elsewhere.
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using namespace InstructionSet::x86;
Does the easier part of the easier half of 8086 decoding.
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Starts building an x86 test.
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// Only 8086 is suppoted for now.
Decoder::Decoder(Model) {}
Adds files for the M50740 and corrects namespace errors elsewhere.
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std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *source, size_t length) {
Finally runs into the wall of trying to merge operands and offsets.
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const uint8_t *const end = source + length;
Does the easier part of the easier half of 8086 decoding.
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Nudges up to a need to decode operation from the ModRegRM byte.
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// MARK: - Prefixes (if present) and the opcode.
Simplifies macros, implements d0, d1, d2 and d3.
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/// Helper macro for those that follow.
#define SetOpSrcDestSize(op, src, dest, size) \
operation_ = Operation::op; \
source_ = Source::src; \
destination_ = Source::dest; \
operation_size_ = size
Nudges up to a need to decode operation from the ModRegRM byte.
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/// Covers anything which is complete as soon as the opcode is encountered.
Simplifies macros, implements d0, d1, d2 and d3.
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#define Complete(op, src, dest, size) \
SetOpSrcDestSize(op, src, dest, size); \
phase_ = Phase::ReadyToPost
Does the easier part of the easier half of 8086 decoding.
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Nudges up to a need to decode operation from the ModRegRM byte.
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/// Handles instructions of the form rr, kk and rr, jjkk, i.e. a destination register plus an operand.
Simplifies macros, implements d0, d1, d2 and d3.
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#define RegData(op, dest, size) \
SetOpSrcDestSize(op, DirectAddress, dest, size); \
Ensures that the operand is the only thing failing in decoding of the first instruction.
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source_ = Source::Immediate; \
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
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operand_size_ = size; \
Simplifies macros, implements d0, d1, d2 and d3.
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phase_ = Phase::AwaitingDisplacementOrOperand
Improves exposition, adds decoding of the 0xbx patch of MOVs.
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Nudges up to a need to decode operation from the ModRegRM byte.
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/// Handles instructions of the form Ax, jjkk where the latter is implicitly an address.
Simplifies macros, implements d0, d1, d2 and d3.
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#define RegAddr(op, dest, op_size, addr_size) \
SetOpSrcDestSize(op, DirectAddress, dest, op_size); \
operand_size_ = addr_size; \
phase_ = Phase::AwaitingDisplacementOrOperand
Nudges up to a need to decode operation from the ModRegRM byte.
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/// Handles instructions of the form jjkk, Ax where the former is implicitly an address.
Simplifies macros, implements d0, d1, d2 and d3.
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#define AddrReg(op, source, op_size, addr_size) \
SetOpSrcDestSize(op, source, DirectAddress, op_size); \
operand_size_ = addr_size; \
Completes the first test stream. ... and improves decoding consistency in conjunction.
2021-01-13 02:49:22 +00:00
destination_ = Source::DirectAddress; \
Simplifies macros, implements d0, d1, d2 and d3.
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phase_ = Phase::AwaitingDisplacementOrOperand
Nudges up to a need to decode operation from the ModRegRM byte.
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/// Covers both `mem/reg, reg` and `reg, mem/reg`.
Simplifies macros, implements d0, d1, d2 and d3.
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#define MemRegReg(op, format, size) \
operation_ = Operation::op; \
phase_ = Phase::ModRegRM; \
modregrm_format_ = ModRegRMFormat::format; \
operand_size_ = 0; \
operation_size_ = size
Nudges up to a need to decode operation from the ModRegRM byte.
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/// Handles JO, JNO, JB, etc — jumps with a single byte displacement.
Simplifies macros, implements d0, d1, d2 and d3.
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#define Jump(op) \
operation_ = Operation::op; \
phase_ = Phase::AwaitingDisplacementOrOperand; \
Adds operand/displacement capture. This gets unit test as far as a disagreement over how to handle bad 0xc4 suffixes.
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displacement_size_ = 1
Nudges up to a need to decode operation from the ModRegRM byte.
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/// Handles far CALL and far JMP — fixed four byte operand operations.
Simplifies macros, implements d0, d1, d2 and d3.
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#define Far(op) \
operation_ = Operation::op; \
phase_ = Phase::AwaitingDisplacementOrOperand; \
operand_size_ = 4; \
Does the easier part of the easier half of 8086 decoding.
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Proceeds to three instructions correctly decoded. 'Wow'.
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while(phase_ == Phase::Instruction && source != end) {
Deferring ModRM work, proceeds to 0x9f.
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// Retain the instruction byte, in case additional decoding is deferred
Nudges up to a need to decode operation from the ModRegRM byte.
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// to the ModRegRM byte.
Deferring ModRM work, proceeds to 0x9f.
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instr_ = *source;
Finally runs into the wall of trying to merge operands and offsets.
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++source;
++consumed_;
Deferring ModRM work, proceeds to 0x9f.
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switch(instr_) {
Finally runs into the wall of trying to merge operands and offsets.
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default: {
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
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const auto result = std::make_pair(consumed_, Instruction());
Attempts to consolidate source/destination ordering.
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reset_parsing();
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
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return result;
Finally runs into the wall of trying to merge operands and offsets.
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}
Attempts to consolidate source/destination ordering.
2021-01-03 22:28:29 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
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#define PartialBlock(start, operation) \
case start + 0x00: MemRegReg(operation, MemReg_Reg, 1); break; \
case start + 0x01: MemRegReg(operation, MemReg_Reg, 2); break; \
case start + 0x02: MemRegReg(operation, Reg_MemReg, 1); break; \
case start + 0x03: MemRegReg(operation, Reg_MemReg, 2); break; \
case start + 0x04: RegData(operation, AL, 1); break; \
case start + 0x05: RegData(operation, AX, 2)
Does the easier part of the easier half of 8086 decoding.
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Simplifies macros, implements d0, d1, d2 and d3.
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PartialBlock(0x00, ADD); break;
case 0x06: Complete(PUSH, ES, None, 2); break;
Completes list, ensures POP acts as documented.
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case 0x07: Complete(POP, None, ES, 2); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
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PartialBlock(0x08, OR); break;
case 0x0e: Complete(PUSH, CS, None, 2); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
PartialBlock(0x10, ADC); break;
case 0x16: Complete(PUSH, SS, None, 2); break;
Completes list, ensures POP acts as documented.
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case 0x17: Complete(POP, None, SS, 2); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
PartialBlock(0x18, SBB); break;
case 0x1e: Complete(PUSH, DS, None, 2); break;
Completes list, ensures POP acts as documented.
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case 0x1f: Complete(POP, None, DS, 2); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
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PartialBlock(0x20, AND); break;
case 0x26: segment_override_ = Source::ES; break;
case 0x27: Complete(DAA, AL, AL, 1); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
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PartialBlock(0x28, SUB); break;
case 0x2e: segment_override_ = Source::CS; break;
case 0x2f: Complete(DAS, AL, AL, 1); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
PartialBlock(0x30, XOR); break;
case 0x36: segment_override_ = Source::SS; break;
case 0x37: Complete(AAA, AL, AX, 1); break;
Does the easier part of the easier half of 8086 decoding.
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Simplifies macros, implements d0, d1, d2 and d3.
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PartialBlock(0x38, CMP); break;
case 0x3e: segment_override_ = Source::DS; break;
case 0x3f: Complete(AAS, AL, AX, 1); break;
Does the easier part of the easier half of 8086 decoding.
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#undef PartialBlock
Simplifies macros, implements d0, d1, d2 and d3.
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#define RegisterBlock(start, operation) \
case start + 0x00: Complete(operation, AX, AX, 2); break; \
case start + 0x01: Complete(operation, CX, CX, 2); break; \
case start + 0x02: Complete(operation, DX, DX, 2); break; \
case start + 0x03: Complete(operation, BX, BX, 2); break; \
case start + 0x04: Complete(operation, SP, SP, 2); break; \
case start + 0x05: Complete(operation, BP, BP, 2); break; \
case start + 0x06: Complete(operation, SI, SI, 2); break; \
case start + 0x07: Complete(operation, DI, DI, 2)
RegisterBlock(0x40, INC); break;
RegisterBlock(0x48, DEC); break;
RegisterBlock(0x50, PUSH); break;
RegisterBlock(0x58, POP); break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
#undef RegisterBlock
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// 0x60–0x6f: not used.
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
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case 0x70: Jump(JO); break;
case 0x71: Jump(JNO); break;
case 0x72: Jump(JB); break;
case 0x73: Jump(JNB); break;
case 0x74: Jump(JE); break;
case 0x75: Jump(JNE); break;
case 0x76: Jump(JBE); break;
case 0x77: Jump(JNBE); break;
case 0x78: Jump(JS); break;
case 0x79: Jump(JNS); break;
case 0x7a: Jump(JP); break;
case 0x7b: Jump(JNP); break;
case 0x7c: Jump(JL); break;
case 0x7d: Jump(JNL); break;
case 0x7e: Jump(JLE); break;
case 0x7f: Jump(JNLE); break;
Does the easier part of the easier half of 8086 decoding.
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Implements 80 and 81.
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case 0x80: MemRegReg(Invalid, MemRegADD_to_CMP, 1); break;
case 0x81: MemRegReg(Invalid, MemRegADD_to_CMP, 2); break;
Takes a run at 0x82 and 0x83, completing the set.
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case 0x82: MemRegReg(Invalid, MemRegADC_to_CMP, 1); break;
case 0x83: MemRegReg(Invalid, MemRegADC_to_CMP, 2); break;
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
Simplifies macros, implements d0, d1, d2 and d3.
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case 0x84: MemRegReg(TEST, MemReg_Reg, 1); break;
case 0x85: MemRegReg(TEST, MemReg_Reg, 2); break;
case 0x86: MemRegReg(XCHG, Reg_MemReg, 1); break;
case 0x87: MemRegReg(XCHG, Reg_MemReg, 2); break;
case 0x88: MemRegReg(MOV, MemReg_Reg, 1); break;
case 0x89: MemRegReg(MOV, MemReg_Reg, 2); break;
case 0x8a: MemRegReg(MOV, Reg_MemReg, 1); break;
case 0x8b: MemRegReg(MOV, Reg_MemReg, 2); break;
Nudges up to a need to decode operation from the ModRegRM byte.
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// 0x8c: not used.
Simplifies macros, implements d0, d1, d2 and d3.
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case 0x8d: MemRegReg(LEA, Reg_MemReg, 2); break;
Decodes 8e.
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case 0x8e: MemRegReg(MOV, SegReg, 2); break;
Simplifies macros, implements d0, d1, d2 and d3.
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case 0x8f: MemRegReg(POP, MemRegPOP, 2); break;
case 0x90: Complete(NOP, None, None, 0); break; // Or XCHG AX, AX?
case 0x91: Complete(XCHG, AX, CX, 2); break;
case 0x92: Complete(XCHG, AX, DX, 2); break;
case 0x93: Complete(XCHG, AX, BX, 2); break;
case 0x94: Complete(XCHG, AX, SP, 2); break;
case 0x95: Complete(XCHG, AX, BP, 2); break;
case 0x96: Complete(XCHG, AX, SI, 2); break;
case 0x97: Complete(XCHG, AX, DI, 2); break;
case 0x98: Complete(CBW, AL, AH, 1); break;
case 0x99: Complete(CWD, AX, DX, 2); break;
case 0x9a: Far(CALLF); break;
case 0x9b: Complete(WAIT, None, None, 0); break;
case 0x9c: Complete(PUSHF, None, None, 2); break;
case 0x9d: Complete(POPF, None, None, 2); break;
case 0x9e: Complete(SAHF, None, None, 1); break;
case 0x9f: Complete(LAHF, None, None, 1); break;
case 0xa0: RegAddr(MOV, AL, 1, 1); break;
case 0xa1: RegAddr(MOV, AX, 2, 2); break;
case 0xa2: AddrReg(MOV, AL, 1, 1); break;
case 0xa3: AddrReg(MOV, AX, 2, 2); break;
case 0xa4: Complete(MOVS, None, None, 1); break;
case 0xa5: Complete(MOVS, None, None, 2); break;
case 0xa6: Complete(CMPS, None, None, 1); break;
case 0xa7: Complete(CMPS, None, None, 2); break;
case 0xa8: RegData(TEST, AL, 1); break;
case 0xa9: RegData(TEST, AX, 2); break;
case 0xaa: Complete(STOS, None, None, 1); break;
case 0xab: Complete(STOS, None, None, 2); break;
case 0xac: Complete(LODS, None, None, 1); break;
case 0xad: Complete(LODS, None, None, 2); break;
case 0xae: Complete(SCAS, None, None, 1); break;
case 0xaf: Complete(SCAS, None, None, 2); break;
case 0xb0: RegData(MOV, AL, 1); break;
case 0xb1: RegData(MOV, CL, 1); break;
case 0xb2: RegData(MOV, DL, 1); break;
case 0xb3: RegData(MOV, BL, 1); break;
case 0xb4: RegData(MOV, AH, 1); break;
case 0xb5: RegData(MOV, CH, 1); break;
case 0xb6: RegData(MOV, DH, 1); break;
case 0xb7: RegData(MOV, BH, 1); break;
case 0xb8: RegData(MOV, AX, 2); break;
case 0xb9: RegData(MOV, CX, 2); break;
case 0xba: RegData(MOV, DX, 2); break;
case 0xbb: RegData(MOV, BX, 2); break;
case 0xbc: RegData(MOV, SP, 2); break;
case 0xbd: RegData(MOV, BP, 2); break;
case 0xbe: RegData(MOV, SI, 2); break;
case 0xbf: RegData(MOV, DI, 2); break;
case 0xc2: RegData(RETN, None, 2); break;
case 0xc3: Complete(RETN, None, None, 2); break;
Adds byte-by-byte decoder test; corrects divergences.
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case 0xc4: MemRegReg(LES, Reg_MemReg, 2); break;
case 0xc5: MemRegReg(LDS, Reg_MemReg, 2); break;
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
case 0xc6: MemRegReg(MOV, MemRegMOV, 1); break;
case 0xc7: MemRegReg(MOV, MemRegMOV, 2); break;
case 0xca: RegData(RETF, None, 2); break;
case 0xcb: Complete(RETF, None, None, 4); break;
case 0xcc: Complete(INT3, None, None, 0); break;
case 0xcd: RegData(INT, None, 1); break;
case 0xce: Complete(INTO, None, None, 0); break;
case 0xcf: Complete(IRET, None, None, 0); break;
case 0xd0: case 0xd1:
phase_ = Phase::ModRegRM;
modregrm_format_ = ModRegRMFormat::MemRegROL_to_SAR;
operation_size_ = 1 + (instr_ & 1);
source_ = Source::Immediate;
Marks intent for operand/displacement.
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operand_ = 1;
Simplifies macros, implements d0, d1, d2 and d3.
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break;
case 0xd2: case 0xd3:
phase_ = Phase::ModRegRM;
modregrm_format_ = ModRegRMFormat::MemRegROL_to_SAR;
operation_size_ = 1 + (instr_ & 1);
source_ = Source::CL;
break;
case 0xd4: RegData(AAM, AX, 1); break;
case 0xd5: RegData(AAD, AX, 1); break;
case 0xd7: Complete(XLAT, None, None, 1); break;
case 0xd8: MemRegReg(ESC, MemReg_Reg, 0); break;
case 0xd9: MemRegReg(ESC, MemReg_Reg, 0); break;
case 0xda: MemRegReg(ESC, MemReg_Reg, 0); break;
case 0xdb: MemRegReg(ESC, MemReg_Reg, 0); break;
case 0xdc: MemRegReg(ESC, MemReg_Reg, 0); break;
case 0xdd: MemRegReg(ESC, MemReg_Reg, 0); break;
case 0xde: MemRegReg(ESC, MemReg_Reg, 0); break;
case 0xdf: MemRegReg(ESC, MemReg_Reg, 0); break;
case 0xe0: Jump(LOOPNE); break;
case 0xe1: Jump(LOOPE); break;
case 0xe2: Jump(LOOP); break;
case 0xe3: Jump(JPCX); break;
case 0xe4: RegAddr(IN, AL, 1, 1); break;
case 0xe5: RegAddr(IN, AX, 2, 1); break;
case 0xe6: AddrReg(OUT, AL, 1, 1); break;
case 0xe7: AddrReg(OUT, AX, 2, 1); break;
case 0xe8: RegData(CALLD, None, 2); break;
Attempts to complete operand recognition.
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case 0xe9: RegData(JMPN, None, 2); break;
case 0xea: Far(JMPF); break;
case 0xeb: Jump(JMPN); break;
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
case 0xec: Complete(IN, DX, AL, 1); break;
case 0xed: Complete(IN, DX, AX, 1); break;
case 0xee: Complete(OUT, AL, DX, 1); break;
Adds operand/displacement capture. This gets unit test as far as a disagreement over how to handle bad 0xc4 suffixes.
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case 0xef: Complete(OUT, AX, DX, 2); break;
Simplifies macros, implements d0, d1, d2 and d3.
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case 0xf4: Complete(HLT, None, None, 1); break;
case 0xf5: Complete(CMC, None, None, 1); break;
case 0xf6: MemRegReg(Invalid, MemRegTEST_to_IDIV, 1); break;
case 0xf7: MemRegReg(Invalid, MemRegTEST_to_IDIV, 2); break;
case 0xf8: Complete(CLC, None, None, 1); break;
case 0xf9: Complete(STC, None, None, 1); break;
case 0xfa: Complete(CLI, None, None, 1); break;
case 0xfb: Complete(STI, None, None, 1); break;
case 0xfc: Complete(CLD, None, None, 1); break;
case 0xfd: Complete(STD, None, None, 1); break;
Finally runs into the wall of trying to merge operands and offsets.
2021-01-04 01:08:13 +00:00
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
case 0xfe: MemRegReg(Invalid, MemRegINC_DEC, 1); break;
case 0xff: MemRegReg(Invalid, MemRegINC_to_PUSH, 1); break;
Formalises what's missing in terms of opcodes and fills in some blanks.
2021-01-06 02:47:12 +00:00
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
// Other prefix bytes.
case 0xf0: lock_ = true; break;
case 0xf2: repetition_ = Repetition::RepNE; break;
case 0xf3: repetition_ = Repetition::RepE; break;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
}
}
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
#undef Far
#undef Jump
#undef MemRegReg
#undef AddrReg
#undef RegAddr
#undef RegData
#undef Complete
#undef SetOpSrcDestSize
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// MARK: - ModRegRM byte, if any.
if(phase_ == Phase::ModRegRM && source != end) {
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
const uint8_t mod = *source >> 6; // i.e. mode.
const uint8_t reg = (*source >> 3) & 7; // i.e. register.
const uint8_t rm = *source & 7; // i.e. register/memory.
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
++source;
++consumed_;
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
Source memreg;
constexpr Source reg_table[3][8] = {
{},
{
Source::AL, Source::CL, Source::DL, Source::BL,
Source::AH, Source::CH, Source::DH, Source::BH,
}, {
Source::AX, Source::CX, Source::DX, Source::BX,
Source::SP, Source::BP, Source::SI, Source::DI,
}
};
switch(mod) {
case 0: {
constexpr Source rm_table[8] = {
Source::IndBXPlusSI, Source::IndBXPlusDI,
Source::IndBPPlusSI, Source::IndBPPlusDI,
Source::IndSI, Source::IndDI,
Source::DirectAddress, Source::IndBX,
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
};
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
memreg = rm_table[rm];
} break;
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
default: {
constexpr Source rm_table[8] = {
Source::IndBXPlusSI, Source::IndBXPlusDI,
Source::IndBPPlusSI, Source::IndBPPlusDI,
Source::IndSI, Source::IndDI,
Source::IndBP, Source::IndBX,
};
memreg = rm_table[rm];
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
displacement_size_ = 1 + (mod == 2);
} break;
// Other operand is just a register.
case 3:
memreg = reg_table[operation_size_][rm];
Completes the first test stream. ... and improves decoding consistency in conjunction.
2021-01-13 02:49:22 +00:00
Chips further away at documentation.
2021-01-15 23:52:59 +00:00
// LES and LDS accept a memory argument only, not a register.
Completes the first test stream. ... and improves decoding consistency in conjunction.
2021-01-13 02:49:22 +00:00
if(operation_ == Operation::LES || operation_ == Operation::LDS) {
const auto result = std::make_pair(consumed_, Instruction());
reset_parsing();
return result;
}
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
break;
}
switch(modregrm_format_) {
case ModRegRMFormat::Reg_MemReg:
case ModRegRMFormat::MemReg_Reg: {
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
if(modregrm_format_ == ModRegRMFormat::Reg_MemReg) {
source_ = memreg;
destination_ = reg_table[operation_size_][reg];
} else {
source_ = reg_table[operation_size_][reg];
destination_ = memreg;
}
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
} break;
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
case ModRegRMFormat::MemRegTEST_to_IDIV:
source_ = destination_ = memreg;
switch(reg) {
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
default: {
const auto result = std::make_pair(consumed_, Instruction());
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
reset_parsing();
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
return result;
}
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
case 0: operation_ = Operation::TEST; break;
case 2: operation_ = Operation::NOT; break;
case 3: operation_ = Operation::NEG; break;
case 4: operation_ = Operation::MUL; break;
case 5: operation_ = Operation::IMUL; break;
case 6: operation_ = Operation::DIV; break;
case 7: operation_ = Operation::IDIV; break;
}
break;
Decodes 8e.
2021-01-08 02:36:05 +00:00
case ModRegRMFormat::SegReg: {
source_ = memreg;
constexpr Source seg_table[4] = {
Source::ES, Source::CS,
Source::SS, Source::DS,
};
if(reg & 4) {
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
const auto result = std::make_pair(consumed_, Instruction());
Decodes 8e.
2021-01-08 02:36:05 +00:00
reset_parsing();
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
return result;
Decodes 8e.
2021-01-08 02:36:05 +00:00
}
destination_ = seg_table[reg];
} break;
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
case ModRegRMFormat::MemRegROL_to_SAR:
destination_ = memreg;
switch(reg) {
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
default: {
const auto result = std::make_pair(consumed_, Instruction());
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
reset_parsing();
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
return result;
}
Simplifies macros, implements d0, d1, d2 and d3.
2021-01-08 02:30:01 +00:00
case 0: operation_ = Operation::ROL; break;
case 2: operation_ = Operation::ROR; break;
case 3: operation_ = Operation::RCL; break;
case 4: operation_ = Operation::RCR; break;
case 5: operation_ = Operation::SAL; break;
case 6: operation_ = Operation::SHR; break;
case 7: operation_ = Operation::SAR; break;
}
break;
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
case ModRegRMFormat::MemRegINC_DEC:
source_ = destination_ = memreg;
switch(reg) {
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
default: {
const auto result = std::make_pair(consumed_, Instruction());
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
reset_parsing();
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
return result;
}
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
case 0: operation_ = Operation::INC; break;
case 1: operation_ = Operation::DEC; break;
}
break;
case ModRegRMFormat::MemRegINC_to_PUSH:
source_ = destination_ = memreg;
switch(reg) {
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
default: {
const auto result = std::make_pair(consumed_, Instruction());
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
reset_parsing();
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
return result;
}
Attempts to complete operand recognition.
2021-01-08 02:59:00 +00:00
case 0: operation_ = Operation::INC; break;
case 1: operation_ = Operation::DEC; break;
case 2: operation_ = Operation::CALLN; break;
case 3:
operation_ = Operation::CALLF;
operand_size_ = 4;
source_ = Source::Immediate;
break;
case 4: operation_ = Operation::JMPN; break;
case 5:
operation_ = Operation::JMPF;
operand_size_ = 4;
source_ = Source::Immediate;
break;
case 6: operation_ = Operation::PUSH; break;
}
break;
Fills in 8f, c2, c3, ca and cb. Also switches to RETN and RETF for near/far RET as this seems idiomatic.
2021-01-07 02:18:24 +00:00
case ModRegRMFormat::MemRegPOP:
source_ = destination_ = memreg;
if(reg != 0) {
reset_parsing();
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
return std::make_pair(consumed_, Instruction());
Fills in 8f, c2, c3, ca and cb. Also switches to RETN and RETF for near/far RET as this seems idiomatic.
2021-01-07 02:18:24 +00:00
}
break;
case ModRegRMFormat::MemRegMOV:
source_ = Source::Immediate;
destination_ = memreg;
operand_size_ = operation_size_;
break;
Implements 80 and 81.
2021-01-09 03:50:59 +00:00
case ModRegRMFormat::MemRegADD_to_CMP:
destination_ = memreg;
operand_size_ = operation_size_;
switch(reg) {
default: operation_ = Operation::ADD; break;
case 1: operation_ = Operation::OR; break;
case 2: operation_ = Operation::ADC; break;
case 3: operation_ = Operation::SBB; break;
case 4: operation_ = Operation::AND; break;
case 5: operation_ = Operation::SUB; break;
case 6: operation_ = Operation::XOR; break;
case 7: operation_ = Operation::CMP; break;
}
break;
Takes a run at 0x82 and 0x83, completing the set.
2021-01-14 01:29:44 +00:00
case ModRegRMFormat::MemRegADC_to_CMP:
destination_ = memreg;
source_ = Source::Immediate;
operand_size_ = 1; // ... and always 1; it'll be sign extended if
// the operation requires it.
switch(reg) {
default: {
const auto result = std::make_pair(consumed_, Instruction());
reset_parsing();
return result;
}
case 0: operation_ = Operation::ADD; break;
case 2: operation_ = Operation::ADC; break;
case 3: operation_ = Operation::SBB; break;
case 5: operation_ = Operation::SUB; break;
case 7: operation_ = Operation::CMP; break;
}
break;
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
default: assert(false);
}
Ostensibly gets the instruction stream correct for test case 1. Subject to operand and displacement currently being absent, and likely inconsistencies in field population, most of which are omitted from the Instruction anyway.
2021-01-06 02:34:35 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
phase_ = (displacement_size_ + operand_size_) ? Phase::AwaitingDisplacementOrOperand : Phase::ReadyToPost;
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
}
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// MARK: - Displacement and operand.
if(phase_ == Phase::AwaitingDisplacementOrOperand && source != end) {
const int required_bytes = displacement_size_ + operand_size_;
Proceeds to three instructions correctly decoded. 'Wow'.
2021-01-03 22:03:50 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
const int outstanding_bytes = required_bytes - operand_bytes_;
const int bytes_to_consume = std::min(int(end - source), outstanding_bytes);
Marks intent for operand/displacement.
2021-01-09 03:45:27 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
// TODO: I can surely do better than this?
for(int c = 0; c < bytes_to_consume; c++) {
inward_data_ = (inward_data_ >> 8) | (uint64_t(source[0]) << 56);
++source;
}
Marks intent for operand/displacement.
2021-01-09 03:45:27 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
consumed_ += bytes_to_consume;
operand_bytes_ += bytes_to_consume;
Marks intent for operand/displacement.
2021-01-09 03:45:27 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
if(bytes_to_consume == outstanding_bytes) {
phase_ = Phase::ReadyToPost;
Adds operand/displacement capture. This gets unit test as far as a disagreement over how to handle bad 0xc4 suffixes.
2021-01-11 03:55:25 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
switch(operand_size_) {
default: operand_ = 0; break;
case 1:
operand_ = inward_data_ >> 56; inward_data_ <<= 8;
Takes a run at 0x82 and 0x83, completing the set.
2021-01-14 01:29:44 +00:00
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
// Sign extend if a single byte operand is feeding a two-byte instruction.
if(operation_size_ == 2 && operation_ != Operation::IN && operation_ != Operation::OUT) {
operand_ |= (operand_ & 0x80) ? 0xff00 : 0x0000;
}
break;
Introduces 'far' test, fixes parsing.
2021-01-15 03:15:38 +00:00
case 4: displacement_size_ = 2; [[fallthrough]];
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
case 2: operand_ = inward_data_ >> 48; inward_data_ <<= 16; break;
Introduces 'far' test, fixes parsing.
2021-01-15 03:15:38 +00:00
break;
Marks intent for operand/displacement.
2021-01-09 03:45:27 +00:00
}
Adds byte-by-byte decoder test; corrects divergences.
2021-01-14 02:51:18 +00:00
switch(displacement_size_) {
default: displacement_ = 0; break;
case 1: displacement_ = int8_t(inward_data_ >> 56); break;
case 2: displacement_ = int16_t(inward_data_ >> 48); break;
}
} else {
// Provide a genuine measure of further bytes required.
return std::make_pair(-(outstanding_bytes - bytes_to_consume), Instruction());
Proceeds to three instructions correctly decoded. 'Wow'.
2021-01-03 22:03:50 +00:00
}
Muddles drunkenly towards decoding ModRM.
2021-01-03 02:11:19 +00:00
}
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// MARK: - Check for completion.
Attempts to consolidate source/destination ordering.
2021-01-03 22:28:29 +00:00
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
if(phase_ == Phase::ReadyToPost) {
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
const auto result = std::make_pair(
consumed_,
Instruction(
operation_,
source_,
destination_,
lock_,
segment_override_,
repetition_,
Size(operation_size_),
Edges closer towards full x86 recording.
2021-01-09 03:38:56 +00:00
displacement_,
operand_)
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
);
Attempts to consolidate source/destination ordering.
2021-01-03 22:28:29 +00:00
reset_parsing();
Proceeds to three instructions correctly decoded. 'Wow'.
2021-01-03 22:03:50 +00:00
return result;
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
}
Nudges up to a need to decode operation from the ModRegRM byte.
2021-01-06 02:25:12 +00:00
// i.e. not done yet.
Rethinks `size`; packs all captured information into an x86 Instruction. Albeit that operand and displacement are't yet captured. Or extractable.
2021-01-09 03:22:07 +00:00
return std::make_pair(0, Instruction());
Does the easier part of the easier half of 8086 decoding.
2021-01-03 00:16:07 +00:00
}
Reference in New Issue Copy Permalink