2024-03-20 18:25:20 +00:00
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//
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// Video.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 20/03/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "../../../Outputs/Log.hpp"
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2024-03-22 00:41:24 +00:00
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#include "../../../Outputs/CRT/CRT.hpp"
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2024-03-20 18:25:20 +00:00
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2024-03-22 14:18:25 +00:00
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#include <array>
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2024-03-20 18:25:20 +00:00
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#include <cstdint>
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2024-03-22 01:53:50 +00:00
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#include <cstring>
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2024-03-20 18:25:20 +00:00
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namespace Archimedes {
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2024-03-22 14:01:34 +00:00
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template <typename InterruptObserverT, typename ClockRateObserverT, typename SoundT>
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struct Video {
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Video(InterruptObserverT &interrupt_observer, ClockRateObserverT &clock_rate_observer, SoundT &sound, const uint8_t *ram) :
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interrupt_observer_(interrupt_observer),
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clock_rate_observer_(clock_rate_observer),
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2024-03-22 00:41:24 +00:00
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sound_(sound),
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ram_(ram),
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crt_(Outputs::Display::InputDataType::Red4Green4Blue4) {
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set_clock_divider(3);
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}
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2024-03-20 18:43:47 +00:00
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2024-03-20 18:25:20 +00:00
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void write(uint32_t value) {
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const auto target = (value >> 24) & 0xfc;
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2024-03-21 14:02:56 +00:00
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const auto timing_value = [](uint32_t value) -> uint32_t {
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return (value >> 14) & 0x3ff;
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};
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const auto colour = [](uint32_t value) -> uint16_t {
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uint8_t packed[2];
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packed[0] = value & 0xf;
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packed[1] = (value & 0xf0) | ((value & 0xf00) >> 8);
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uint16_t result;
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memcpy(&result, packed, 2);
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return result;
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};
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switch(target) {
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case 0x00: case 0x04: case 0x08: case 0x0c:
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case 0x10: case 0x14: case 0x18: case 0x1c:
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case 0x20: case 0x24: case 0x28: case 0x2c:
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case 0x30: case 0x34: case 0x38: case 0x3c:
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colours_[target >> 2] = colour(value);
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break;
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case 0x40: border_colour_ = colour(value); break;
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2024-03-20 18:25:20 +00:00
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case 0x44: case 0x48: case 0x4c:
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logger.error().append("TODO: Cursor colour %d to %03x", (target - 0x44) >> 2, value & 0x1fff);
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break;
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2024-03-22 01:40:11 +00:00
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case 0x80: horizontal_timing_.period = timing_value(value); break;
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case 0x84: horizontal_timing_.sync_width = timing_value(value); break;
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case 0x88: horizontal_timing_.border_start = timing_value(value); break;
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case 0x8c: horizontal_timing_.display_start = timing_value(value); break;
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case 0x90: horizontal_timing_.display_end = timing_value(value); break;
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case 0x94: horizontal_timing_.border_end = timing_value(value); break;
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case 0x98: horizontal_timing_.cursor_end = timing_value(value); break;
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case 0x9c:
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logger.error().append("TODO: Video horizontal interlace: %d", (value >> 14) & 0x3ff);
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break;
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2024-03-22 01:40:11 +00:00
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case 0xa0: vertical_timing_.period = timing_value(value); break;
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case 0xa4: vertical_timing_.sync_width = timing_value(value); break;
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case 0xa8: vertical_timing_.border_start = timing_value(value); break;
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case 0xac: vertical_timing_.display_start = timing_value(value); break;
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case 0xb0: vertical_timing_.display_end = timing_value(value); break;
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case 0xb4: vertical_timing_.border_end = timing_value(value); break;
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case 0xb8: vertical_timing_.cursor_start = timing_value(value); break;
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case 0xbc: vertical_timing_.cursor_end = timing_value(value); break;
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case 0xe0:
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logger.error().append("TODO: video control: %08x", value);
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2024-03-21 15:03:28 +00:00
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2024-03-21 15:51:29 +00:00
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// Set pixel rate. This is the value that a 24Mhz clock should be divided
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// by to get half the pixel rate.
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switch(value & 0b11) {
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case 0b00: set_clock_divider(6); break; // i.e. pixel clock = 8Mhz.
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case 0b01: set_clock_divider(4); break; // 12Mhz.
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case 0b10: set_clock_divider(3); break; // 16Mhz.
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case 0b11: set_clock_divider(2); break; // 24Mhz.
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}
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break;
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2024-03-20 18:43:47 +00:00
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//
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// Sound parameters.
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//
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case 0x60: case 0x64: case 0x68: case 0x6c:
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case 0x70: case 0x74: case 0x78: case 0x7c: {
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const uint8_t channel = ((value >> 26) + 7) & 7;
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sound_.set_stereo_image(channel, value & 7);
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} break;
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case 0xc0:
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sound_.set_frequency(value & 0x7f);
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break;
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2024-03-20 18:25:20 +00:00
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default:
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logger.error().append("TODO: unrecognised VIDC write of %08x", value);
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break;
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}
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}
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void tick() {
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// Pick new horizontal state, possibly rolling over into the vertical.
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horizontal_state_.increment_position();
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horizontal_state_.phase =
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horizontal_timing_.phase_after(
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horizontal_state_.position,
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horizontal_state_.phase);
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if(horizontal_state_.position == horizontal_timing_.period ) {
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horizontal_state_.position = 0;
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vertical_state_.increment_position();
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vertical_state_.phase =
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vertical_timing_.phase_after(
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vertical_state_.position,
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vertical_state_.phase);
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if(vertical_state_.position == vertical_timing_.period) {
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vertical_state_.position = 0;
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address_ = frame_start_;
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entered_sync_ = true;
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interrupt_observer_.update_interrupts();
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}
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}
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// Accumulate total phase.
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++time_in_phase_;
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// Grab some more pixels if appropriate.
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const auto flush_pixels = [&]() {
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const auto duration = static_cast<int>(time_in_phase_);
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crt_.output_data(duration, static_cast<size_t>(time_in_phase_));
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time_in_phase_ = 0;
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pixels_ = nullptr;
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};
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if(phase_ == Phase::Display) {
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if(pixels_ && time_in_phase_ == PixelBufferSize) {
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flush_pixels();
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}
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if(!pixels_) {
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if(time_in_phase_) {
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flush_pixels();
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}
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pixels_ = reinterpret_cast<uint16_t *>(crt_.begin_data(PixelBufferSize));
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}
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if(pixels_) {
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// Each tick in here is two ticks of the pixel clock, so:
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//
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// 8bpp mode: output two bytes;
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// 4bpp mode: output one byte;
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// 2bpp mode: output one byte every second tick;
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// 1bpp mode: output one byte every fourth tick.
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// TODO: don't assume 4bpp.
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const uint8_t next = ram_[address_];
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++address_;
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if(address_ == buffer_end_) address_ = buffer_start_;
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pixels_[0] = colours_[next & 0xf];
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pixels_[1] = colours_[next >> 4];
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pixels_ += 2;
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2024-03-23 02:01:12 +00:00
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} else {
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// TODO: don't assume 4bpp here either.
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++address_;
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if(address_ == buffer_end_) address_ = buffer_start_;
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}
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}
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// Determine current output phase.
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Phase new_phase;
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switch(vertical_state_.phase) {
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case Phase::Sync: new_phase = Phase::Sync; break;
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case Phase::Blank: new_phase = Phase::Blank; break;
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2024-03-22 01:29:53 +00:00
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case Phase::Border:
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new_phase = horizontal_state_.phase == Phase::Display ? Phase::Border : horizontal_state_.phase;
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break;
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case Phase::Display:
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new_phase = horizontal_state_.phase;
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break;
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}
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// Possibly output something.
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if(new_phase != phase_) {
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if(time_in_phase_) {
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const auto duration = static_cast<int>(time_in_phase_);
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switch(phase_) {
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case Phase::Sync: crt_.output_sync(duration); break;
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case Phase::Blank: crt_.output_blank(duration); break;
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case Phase::Display: flush_pixels(); break;
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case Phase::Border: crt_.output_level<uint16_t>(duration, border_colour_); break;
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}
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time_in_phase_ = 0;
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}
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phase_ = new_phase;
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}
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}
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2024-03-21 15:51:29 +00:00
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/// @returns @c true if a vertical retrace interrupt has been signalled since the last call to @c interrupt(); @c false otherwise.
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bool interrupt() {
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// Guess: edge triggered?
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const bool interrupt = entered_sync_;
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entered_sync_ = false;
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return interrupt;
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}
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2024-03-21 15:51:29 +00:00
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void set_frame_start(uint32_t address) { frame_start_ = address; }
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void set_buffer_start(uint32_t address) { buffer_start_ = address; }
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void set_buffer_end(uint32_t address) { buffer_end_ = address; }
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void set_cursor_start(uint32_t address) { cursor_start_ = address; }
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2024-03-21 15:24:47 +00:00
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2024-03-22 00:41:24 +00:00
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Outputs::CRT::CRT &crt() { return crt_; }
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const Outputs::CRT::CRT &crt() const { return crt_; }
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int clock_divider() const {
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return static_cast<int>(clock_divider_);
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}
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private:
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Log::Logger<Log::Source::ARMIOC> logger;
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InterruptObserverT &interrupt_observer_;
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ClockRateObserverT &clock_rate_observer_;
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SoundT &sound_;
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2024-03-22 00:22:20 +00:00
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// In the current version of this code, video DMA occurrs costlessly,
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// being deferred to the component itself.
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const uint8_t *ram_ = nullptr;
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2024-03-22 00:41:24 +00:00
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Outputs::CRT::CRT crt_;
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2024-03-22 01:10:55 +00:00
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// Current video state.
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enum class Phase {
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Sync, Blank, Border, Display,
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};
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struct State {
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uint32_t position = 0;
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Phase phase = Phase::Sync;
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2024-03-22 14:01:34 +00:00
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void increment_position() {
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++position;
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if(position == 1024) position = 0;
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}
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};
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State horizontal_state_, vertical_state_;
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Phase phase_ = Phase::Sync;
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uint32_t time_in_phase_ = 0;
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2024-03-22 14:10:13 +00:00
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uint16_t *pixels_ = nullptr;
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static constexpr size_t PixelBufferSize = 320;
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2024-03-22 01:53:50 +00:00
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// Programmer-set addresses.
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uint32_t buffer_start_ = 0;
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uint32_t buffer_end_ = 0;
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uint32_t frame_start_ = 0;
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uint32_t cursor_start_ = 0;
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// Ephemeral address state.
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uint32_t address_ = 0;
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// Horizontal and vertical timing.
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struct Timing {
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uint32_t period = 0;
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uint32_t sync_width = 0;
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uint32_t border_start = 0;
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uint32_t border_end = 0;
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uint32_t display_start = 0;
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uint32_t display_end = 0;
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uint32_t cursor_start = 0;
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uint32_t cursor_end = 0;
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2024-03-22 14:01:34 +00:00
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Phase phase_after(uint32_t position, Phase current_phase) {
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if(position == sync_width) return Phase::Blank;
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if(position == border_start) return Phase::Border;
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if(position == display_start) return Phase::Display;
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if(position == display_end) return Phase::Border;
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if(position == border_end) return Phase::Blank;
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if(position == period) return Phase::Sync;
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return current_phase;
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}
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};
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2024-03-22 01:10:55 +00:00
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Timing horizontal_timing_, vertical_timing_;
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2024-03-21 15:51:29 +00:00
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2024-03-22 01:40:11 +00:00
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// Colour palette, converted to internal format.
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uint16_t border_colour_;
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2024-03-22 14:18:25 +00:00
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std::array<uint16_t, 16> colours_{};
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2024-03-22 01:40:11 +00:00
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2024-03-21 15:51:29 +00:00
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// An interrupt flag; more closely related to the interface by which
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// my implementation of the IOC picks up an interrupt request than
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// to hardware.
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2024-03-21 14:02:56 +00:00
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bool entered_sync_ = false;
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2024-03-21 15:03:28 +00:00
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2024-03-21 15:51:29 +00:00
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// The divider that would need to be applied to a 24Mhz clock to
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// get half the current pixel clock; counting is in units of half
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// the pixel clock because that's the fidelity at which the programmer
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// places horizontal events — display start, end, sync period, etc.
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uint32_t clock_divider_ = 0;
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2024-03-22 00:41:24 +00:00
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void set_clock_divider(uint32_t divider) {
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if(divider == clock_divider_) {
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return;
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}
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clock_divider_ = divider;
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2024-03-22 01:29:53 +00:00
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const auto cycles_per_line = static_cast<int>(24'000'000 / (divider * 312 * 50));
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2024-03-22 00:41:24 +00:00
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crt_.set_new_timing(
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2024-03-22 01:29:53 +00:00
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cycles_per_line,
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2024-03-22 00:41:24 +00:00
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312, /* Height of display. */
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2024-03-22 00:43:55 +00:00
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Outputs::CRT::PAL::ColourSpace,
|
2024-03-22 00:41:24 +00:00
|
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|
Outputs::CRT::PAL::ColourCycleNumerator,
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|
Outputs::CRT::PAL::ColourCycleDenominator,
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|
|
|
Outputs::CRT::PAL::VerticalSyncLength,
|
2024-03-22 00:43:55 +00:00
|
|
|
Outputs::CRT::PAL::AlternatesPhase);
|
2024-03-22 14:01:34 +00:00
|
|
|
clock_rate_observer_.update_clock_rates();
|
2024-03-22 00:41:24 +00:00
|
|
|
}
|
2024-03-20 18:25:20 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
}
|