2022-05-16 15:44:16 +00:00
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//
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// 68000Mk2Storage.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef _8000Mk2Storage_h
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#define _8000Mk2Storage_h
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2022-05-16 20:57:40 +00:00
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#include "../../../InstructionSets/M68k/Status.hpp"
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#include "../../../InstructionSets/M68k/Decoder.hpp"
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2022-05-16 15:44:16 +00:00
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namespace CPU {
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namespace MC68000Mk2 {
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struct ProcessorBase {
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2022-05-16 15:59:03 +00:00
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enum State: int {
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2022-05-16 20:57:40 +00:00
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Reset = -1,
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2022-05-17 12:26:35 +00:00
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Decode = -2,
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2022-05-16 20:57:40 +00:00
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WaitForDTACK = -3,
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2022-05-17 12:26:35 +00:00
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FetchOperand = -4,
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2022-05-16 15:59:03 +00:00
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};
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2022-05-17 00:04:13 +00:00
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int state_ = State::Reset;
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2022-05-16 15:44:16 +00:00
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2022-05-16 20:57:40 +00:00
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HalfCycles time_remaining_;
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int post_dtack_state_ = 0;
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int is_supervisor_ = 1;
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InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder_;
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InstructionSet::M68k::Preinstruction instruction_;
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uint16_t opcode_;
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uint8_t operand_flags_;
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InstructionSet::M68k::Status status_;
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SlicedInt32 program_counter_;
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SlicedInt32 registers_[16]; // D0–D7 followed by A0–A7.
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SlicedInt32 stack_pointers_[2];
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bool dtack_ = false;
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bool vpa_ = false;
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bool berr_ = false;
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2022-05-17 12:26:35 +00:00
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SlicedInt32 prefetch_;
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int operand_ = 0;
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2022-05-16 15:44:16 +00:00
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};
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}
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}
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#endif /* _8000Mk2Storage_h */
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