2020-12-31 03:55:59 +00:00
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//
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2021-01-15 23:16:01 +00:00
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// Decoder.cpp
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2020-12-31 03:55:59 +00:00
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// Clock Signal
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//
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2021-01-17 03:09:19 +00:00
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// Created by Thomas Harte on 30/12/20.
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2020-12-31 03:55:59 +00:00
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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2021-01-15 23:16:01 +00:00
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#include "Decoder.hpp"
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2020-12-31 03:55:59 +00:00
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2021-01-16 02:30:30 +00:00
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using namespace InstructionSet::PowerPC;
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2020-12-31 03:55:59 +00:00
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2022-04-05 15:23:54 +00:00
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namespace {
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2020-12-31 03:55:59 +00:00
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2022-04-05 15:23:54 +00:00
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template <Model model, bool validate_reserved_bits, Operation operation> Instruction instruction(uint32_t opcode, bool is_supervisor = false) {
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// If validation isn't required, there's nothing to do here.
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if constexpr (!validate_reserved_bits) {
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return Instruction(operation, opcode, is_supervisor);
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}
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// Otherwise, validation depends on operation
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// (and, in principle, processor model).
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2022-04-07 01:09:58 +00:00
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switch(operation) {
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2022-04-08 13:47:04 +00:00
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case Operation::absx: case Operation::clcs:
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case Operation::nabsx:
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2022-04-07 01:09:58 +00:00
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case Operation::addmex: case Operation::addzex:
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case Operation::bcctrx: case Operation::bclrx:
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case Operation::cntlzdx: case Operation::cntlzwx:
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case Operation::extsbx: case Operation::extshx: case Operation::extswx:
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case Operation::fmulx: case Operation::fmulsx:
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case Operation::negx:
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case Operation::subfmex: case Operation::subfzex:
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if(opcode & 0b000000'00000'00000'11111'0000000000'0) return Instruction(opcode);
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break;
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case Operation::cmp: case Operation::cmpl:
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if(opcode & 0b000000'00010'00000'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::cmpi: case Operation::cmpli:
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if(opcode & 0b000000'00010'00000'00000'0000000000'0) return Instruction(opcode);
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break;
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case Operation::dcbf: case Operation::dcbi: case Operation::dcbst:
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case Operation::dcbt: case Operation::dcbtst: case Operation::dcbz:
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if(opcode & 0b000000'11111'00000'00000'0000000000'0) return Instruction(opcode);
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break;
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case Operation::crand: case Operation::crandc: case Operation::creqv:
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case Operation::crnand: case Operation::crnor: case Operation::cror:
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case Operation::crorc: case Operation::crxor:
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case Operation::eciwx: case Operation::ecowx:
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case Operation::lbzux: case Operation::lbzx:
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case Operation::ldarx:
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case Operation::ldux: case Operation::ldx:
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case Operation::lfdux: case Operation::lfdx:
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case Operation::lfsux: case Operation::lfsx:
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case Operation::lhaux: case Operation::lhax: case Operation::lhbrx:
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case Operation::lhzux: case Operation::lhzx:
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case Operation::lswi: case Operation::lswx:
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case Operation::lwarx: case Operation::lwaux: case Operation::lwax: case Operation::lwbrx:
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case Operation::lwzux: case Operation::lwzx:
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case Operation::mfspr: case Operation::mftb:
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case Operation::mtspr:
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case Operation::stbux: case Operation::stbx:
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case Operation::stdux: case Operation::stdx:
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case Operation::stfdux: case Operation::stfdx:
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case Operation::stfiwx:
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case Operation::stfsux: case Operation::stfsx:
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case Operation::sthbrx:
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case Operation::sthux: case Operation::sthx:
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case Operation::stswi: case Operation::stswx:
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case Operation::stwbrx:
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case Operation::stwux: case Operation::stwx:
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case Operation::td: case Operation::tw:
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if(opcode & 0b000000'00000'00000'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::fabsx: case Operation::fcfidx:
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case Operation::fctidx: case Operation::fctidzx:
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case Operation::fctiwx: case Operation::fctiwzx:
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case Operation::fmrx: case Operation::fnabsx:
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case Operation::fnegx: case Operation::frspx:
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if(opcode & 0b000000'00000'11111'00000'0000000000'0) return Instruction(opcode);
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break;
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case Operation::faddx: case Operation::faddsx:
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case Operation::fdivx: case Operation::fdivsx:
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case Operation::fsubx: case Operation::fsubsx:
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if(opcode & 0b000000'00000'00000'00000'1111100000'0) return Instruction(opcode);
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break;
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case Operation::fcmpo: case Operation::fcmpu:
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if(opcode & 0b000000'00011'00000'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::fresx: case Operation::frsqrtex:
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case Operation::fsqrtx: case Operation::fsqrtsx:
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if(opcode & 0b000000'00000'11111'00000'1111100000'1) return Instruction(opcode);
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break;
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case Operation::icbi:
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if(opcode & 0b000000'11111'00000'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::eieio:
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case Operation::isync:
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case Operation::rfi:
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case Operation::slbia:
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case Operation::sync:
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case Operation::tlbia:
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case Operation::tlbsync:
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if(opcode & 0b000000'11111'11111'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mcrf: case Operation::mcrfs:
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if(opcode & 0b000000'00011'00011'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mcrxr:
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if(opcode & 0b000000'00011'11111'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mfcr:
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case Operation::mfmsr:
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case Operation::mtmsr:
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if(opcode & 0b000000'00000'11111'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mffsx:
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case Operation::mtfsb0x:
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case Operation::mtfsb1x:
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if(opcode & 0b000000'00000'11111'11111'0000000000'0) return Instruction(opcode);
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break;
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case Operation::mtfsfx:
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if(opcode & 0b000000'10000'00001'00000'0000000000'0) return Instruction(opcode);
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break;
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case Operation::mtfsfix:
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if(opcode & 0b000000'00011'11111'00001'0000000000'0) return Instruction(opcode);
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break;
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case Operation::mtsr:
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if(opcode & 0b000000'00000'10000'11111'0000000000'1) return Instruction(opcode);
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break;
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2022-04-08 13:47:04 +00:00
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case Operation::mtsrin: case Operation::mfsrin:
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2022-04-07 01:09:58 +00:00
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if(opcode & 0b000000'00000'11111'00000'0000000000'1) return Instruction(opcode);
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break;
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2022-04-08 13:47:04 +00:00
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case Operation::mfsr:
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if(opcode & 0b000000'00000'10000'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mtcrf:
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if(opcode & 0b000000'00000'10000'00001'0000000000'1) return Instruction(opcode);
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break;
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2022-04-07 01:09:58 +00:00
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case Operation::mulhdx: case Operation::mulhdux:
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case Operation::mulhwx: case Operation::mulhwux:
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if(opcode & 0b000000'00000'00000'00000'1000000000'0) return Instruction(opcode);
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break;
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case Operation::sc:
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if(opcode & 0b000000'11111'11111'11111'1111111110'1) return Instruction(opcode);
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break;
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case Operation::slbie:
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case Operation::tlbie:
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if(opcode & 0b000000'11111'11111'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::stwcx_:
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if(!(opcode & 0b000000'00000'00000'00000'0000000000'1)) return Instruction(opcode);
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break;
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2022-04-08 13:47:04 +00:00
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case Operation::divx: case Operation::divsx:
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case Operation::dozx: case Operation::dozi:
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case Operation::lscbxx:
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case Operation::maskgx: case Operation::maskirx:
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case Operation::mulx:
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case Operation::rlmix: case Operation::rribx:
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case Operation::slex: case Operation::sleqx: case Operation::sliqx:
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case Operation::slliqx: case Operation::sllqx: case Operation::slqx:
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case Operation::sraiqx: case Operation::sraqx:
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case Operation::srex: case Operation::sreqx:
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case Operation::sriqx: case Operation::srliqx:
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case Operation::srlqx: case Operation::srqx:
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case Operation::sreax:
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2022-04-07 01:09:58 +00:00
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case Operation::addx: case Operation::addcx: case Operation::addex:
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case Operation::addi: case Operation::addic: case Operation::addic_:
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case Operation::addis:
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case Operation::andx: case Operation::andcx:
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case Operation::andi_: case Operation::andis_:
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case Operation::bx: case Operation::bcx:
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case Operation::divdx: case Operation::divdux:
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case Operation::divwx: case Operation::divwux:
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case Operation::eqvx:
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case Operation::fmaddx: case Operation::fmaddsx:
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case Operation::fmsubx: case Operation::fmsubsx:
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case Operation::fnmaddx: case Operation::fnmaddsx:
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case Operation::fnmsubx: case Operation::fnmsubsx:
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case Operation::fselx:
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case Operation::lbz: case Operation::lbzu:
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case Operation::lfd: case Operation::lfdu:
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case Operation::lfs: case Operation::lfsu:
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case Operation::lha: case Operation::lhau:
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case Operation::lhz: case Operation::lhzu:
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case Operation::lmw: case Operation::lwa:
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case Operation::lwz: case Operation::lwzu:
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2022-04-09 22:28:51 +00:00
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case Operation::mulldx: case Operation::mulli: case Operation::mullwx:
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2022-04-07 01:09:58 +00:00
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case Operation::nandx: case Operation::norx:
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case Operation::orx: case Operation::orcx:
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case Operation::ori: case Operation::oris:
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case Operation::rlwimix: case Operation::rlwinmx: case Operation::rlwnmx:
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case Operation::sldx: case Operation::slwx:
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case Operation::sradx: case Operation::sradix:
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case Operation::srawx: case Operation::srawix:
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case Operation::srdx: case Operation::srwx:
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case Operation::stb: case Operation::stbu:
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case Operation::std: case Operation::stdcx_: case Operation::stdu:
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case Operation::stfd: case Operation::stfdu:
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case Operation::stfs: case Operation::stfsu:
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case Operation::sth: case Operation::sthu:
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case Operation::stmw:
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case Operation::stw: case Operation::stwu:
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case Operation::subfx: case Operation::subfcx: case Operation::subfex:
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case Operation::subfic:
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case Operation::tdi: case Operation::twi:
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case Operation::xorx: case Operation::xori: case Operation::xoris:
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2022-04-09 22:28:51 +00:00
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case Operation::ld: case Operation::ldu:
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case Operation::rldclx: case Operation::rldcrx:
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case Operation::rldicx: case Operation::rldiclx:
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case Operation::rldicrx: case Operation::rldimix:
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2022-04-07 01:09:58 +00:00
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break;
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}
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2022-04-05 15:23:54 +00:00
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return Instruction(operation, opcode, is_supervisor);
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}
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}
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template <Model model, bool validate_reserved_bits>
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Instruction Decoder<model, validate_reserved_bits>::decode(uint32_t opcode) {
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2020-12-31 21:02:52 +00:00
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// Quick bluffer's guide to PowerPC instruction encoding:
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//
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// There is a six-bit field at the very top of the instruction.
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// Sometimes that fully identifies an instruction, but usually
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// it doesn't.
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//
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// There is an addition 9- or 10-bit field starting one bit above
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// least significant that disambiguates the rest. Strictly speaking
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// it's a 10-bit field, but the mnemonics for many instructions treat
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// it as a 9-bit field with a flag at the top.
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//
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// I've decided to hew directly to the mnemonics.
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2021-01-01 16:46:26 +00:00
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//
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// Various opcodes in the 1995 documentation define reserved bits,
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// which are given the nominal value of 0. It does not give a formal
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// definition of a reserved bit. As a result this code does not
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// currently check the value of reserved bits. That may need to change
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// if/when I add support for extended instruction sets.
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2020-12-31 21:02:52 +00:00
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2022-04-05 15:23:54 +00:00
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#define Bind(mask, operation) case mask: return instruction<model, validate_reserved_bits, Operation::operation>(opcode);
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#define BindSupervisor(mask, operation) case mask: return instruction<model, validate_reserved_bits, Operation::operation>(opcode, true);
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2020-12-31 21:02:52 +00:00
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#define BindConditional(condition, mask, operation) \
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case mask: \
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2022-04-05 15:23:54 +00:00
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if(condition(model)) return instruction<model, validate_reserved_bits, Operation::operation>(opcode); \
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return instruction<model, validate_reserved_bits, Operation::operation>(opcode);
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2020-12-31 23:14:38 +00:00
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#define BindSupervisorConditional(condition, mask, operation) \
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case mask: \
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2022-04-05 15:23:54 +00:00
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if(condition(model)) return instruction<model, validate_reserved_bits, Operation::operation>(opcode, true); \
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return instruction<model, validate_reserved_bits, Operation::operation>(opcode);
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2020-12-31 21:02:52 +00:00
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2020-12-31 21:51:31 +00:00
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#define Six(x) (unsigned(x) << 26)
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2021-01-01 16:46:26 +00:00
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#define SixTen(x, y) (Six(x) | ((y) << 1))
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2020-12-31 21:02:52 +00:00
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// First pass: weed out all those instructions identified entirely by the
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// top six bits.
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switch(opcode & Six(0b111111)) {
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default: break;
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BindConditional(is64bit, Six(0b000010), tdi);
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Bind(Six(0b000011), twi);
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Bind(Six(0b000111), mulli);
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Bind(Six(0b001000), subfic);
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Bind(Six(0b001100), addic); Bind(Six(0b001101), addic_);
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Bind(Six(0b001110), addi); Bind(Six(0b001111), addis);
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2021-01-03 03:47:42 +00:00
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case Six(0b010000): {
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// This might be a bcx, but check for a valid bo field.
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switch((opcode >> 21) & 0x1f) {
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case 0: case 1: case 2: case 3: case 4: case 5:
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case 8: case 9: case 10: case 11: case 12: case 13:
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case 16: case 17: case 18: case 19: case 20:
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2022-04-05 15:23:54 +00:00
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return instruction<model, validate_reserved_bits, Operation::bcx>(opcode);
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2021-01-03 03:47:42 +00:00
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default: return Instruction(opcode);
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}
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} break;
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2020-12-31 21:02:52 +00:00
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Bind(Six(0b010010), bx);
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Bind(Six(0b010100), rlwimix);
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Bind(Six(0b010101), rlwinmx);
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Bind(Six(0b010111), rlwnmx);
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Bind(Six(0b011000), ori); Bind(Six(0b011001), oris);
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Bind(Six(0b011010), xori); Bind(Six(0b011011), xoris);
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Bind(Six(0b011100), andi_); Bind(Six(0b011101), andis_);
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Bind(Six(0b100000), lwz); Bind(Six(0b100001), lwzu);
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Bind(Six(0b100010), lbz); Bind(Six(0b100011), lbzu);
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Bind(Six(0b100100), stw); Bind(Six(0b100101), stwu);
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Bind(Six(0b100110), stb); Bind(Six(0b100111), stbu);
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Bind(Six(0b101000), lhz); Bind(Six(0b101001), lhzu);
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Bind(Six(0b101010), lha); Bind(Six(0b101011), lhau);
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Bind(Six(0b101100), sth); Bind(Six(0b101101), sthu);
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Bind(Six(0b101110), lmw); Bind(Six(0b101111), stmw);
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Bind(Six(0b110000), lfs); Bind(Six(0b110001), lfsu);
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Bind(Six(0b110010), lfd); Bind(Six(0b110011), lfdu);
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Bind(Six(0b110100), stfs); Bind(Six(0b110101), stfsu);
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Bind(Six(0b110110), stfd); Bind(Six(0b110111), stfdu);
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2021-01-01 16:46:26 +00:00
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BindConditional(is601, Six(9), dozi);
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BindConditional(is601, Six(22), rlmix);
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2020-12-31 21:02:52 +00:00
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Bind(Six(0b001010), cmpli); Bind(Six(0b001011), cmpi);
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2020-12-31 03:55:59 +00:00
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}
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2023-05-12 18:16:39 +00:00
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2020-12-31 21:51:31 +00:00
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// Second pass: all those with a top six bits and a bottom nine or ten.
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switch(opcode & SixTen(0b111111, 0b1111111111)) {
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default: break;
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2021-01-01 16:46:26 +00:00
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// 64-bit instructions.
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BindConditional(is64bit, SixTen(0b011111, 0b0000001001), mulhdux); BindConditional(is64bit, SixTen(0b011111, 0b1000001001), mulhdux);
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2020-12-31 21:51:31 +00:00
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BindConditional(is64bit, SixTen(0b011111, 0b0000010101), ldx);
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BindConditional(is64bit, SixTen(0b011111, 0b0000011011), sldx);
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2020-12-31 23:14:38 +00:00
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BindConditional(is64bit, SixTen(0b011111, 0b0000110101), ldux);
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BindConditional(is64bit, SixTen(0b011111, 0b0000111010), cntlzdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0001000100), td);
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2021-01-01 16:46:26 +00:00
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BindConditional(is64bit, SixTen(0b011111, 0b0001001001), mulhdx); BindConditional(is64bit, SixTen(0b011111, 0b1001001001), mulhdx);
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2020-12-31 23:14:38 +00:00
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BindConditional(is64bit, SixTen(0b011111, 0b0001010100), ldarx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010010101), stdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010110101), stdux);
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2022-04-09 22:28:51 +00:00
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BindConditional(is64bit, SixTen(0b011111, 0b0011101001), mulldx); BindConditional(is64bit, SixTen(0b011111, 0b1011101001), mulldx);
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2020-12-31 23:14:38 +00:00
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BindConditional(is64bit, SixTen(0b011111, 0b0101010101), lwax);
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BindConditional(is64bit, SixTen(0b011111, 0b0101110101), lwaux);
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2021-01-01 16:46:26 +00:00
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BindConditional(is64bit, SixTen(0b011111, 0b1100111011), sradix); BindConditional(is64bit, SixTen(0b011111, 0b1100111010), sradix);
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2020-12-31 23:14:38 +00:00
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BindConditional(is64bit, SixTen(0b011111, 0b0110110010), slbie);
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BindConditional(is64bit, SixTen(0b011111, 0b0111001001), divdux); BindConditional(is64bit, SixTen(0b011111, 0b1111001001), divdux);
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2021-01-01 02:12:36 +00:00
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BindConditional(is64bit, SixTen(0b011111, 0b0111101001), divdx); BindConditional(is64bit, SixTen(0b011111, 0b1111101001), divdx);
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BindConditional(is64bit, SixTen(0b011111, 0b1000011011), srdx);
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BindConditional(is64bit, SixTen(0b011111, 0b1100011010), sradx);
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2022-04-01 21:11:57 +00:00
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BindConditional(is64bit, SixTen(0b111111, 0b1111011010), extswx);
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2021-01-01 16:46:26 +00:00
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// Power instructions; these are all taken from the MPC601 manual rather than
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// the PowerPC Programmer's Reference Guide, hence the decimal encoding of the
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// ten-bit field.
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BindConditional(is601, SixTen(0b011111, 360), absx); BindConditional(is601, SixTen(0b011111, 512 + 360), absx);
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BindConditional(is601, SixTen(0b011111, 531), clcs);
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BindConditional(is601, SixTen(0b011111, 331), divx); BindConditional(is601, SixTen(0b011111, 512 + 331), divx);
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BindConditional(is601, SixTen(0b011111, 363), divsx); BindConditional(is601, SixTen(0b011111, 512 + 363), divsx);
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BindConditional(is601, SixTen(0b011111, 264), dozx); BindConditional(is601, SixTen(0b011111, 512 + 264), dozx);
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BindConditional(is601, SixTen(0b011111, 277), lscbxx);
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BindConditional(is601, SixTen(0b011111, 29), maskgx);
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BindConditional(is601, SixTen(0b011111, 541), maskirx);
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BindConditional(is601, SixTen(0b011111, 107), mulx); BindConditional(is601, SixTen(0b011111, 512 + 107), mulx);
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BindConditional(is601, SixTen(0b011111, 488), nabsx); BindConditional(is601, SixTen(0b011111, 512 + 488), nabsx);
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BindConditional(is601, SixTen(0b011111, 537), rribx);
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BindConditional(is601, SixTen(0b011111, 153), slex);
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BindConditional(is601, SixTen(0b011111, 217), sleqx);
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BindConditional(is601, SixTen(0b011111, 184), sliqx);
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BindConditional(is601, SixTen(0b011111, 248), slliqx);
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BindConditional(is601, SixTen(0b011111, 216), sllqx);
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BindConditional(is601, SixTen(0b011111, 152), slqx);
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BindConditional(is601, SixTen(0b011111, 952), sraiqx);
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BindConditional(is601, SixTen(0b011111, 920), sraqx);
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BindConditional(is601, SixTen(0b011111, 665), srex);
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BindConditional(is601, SixTen(0b011111, 921), sreax);
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BindConditional(is601, SixTen(0b011111, 729), sreqx);
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BindConditional(is601, SixTen(0b011111, 696), sriqx);
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BindConditional(is601, SixTen(0b011111, 760), srliqx);
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BindConditional(is601, SixTen(0b011111, 728), srlqx);
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BindConditional(is601, SixTen(0b011111, 664), srqx);
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2020-12-31 21:51:31 +00:00
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2021-01-01 16:46:26 +00:00
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// 32-bit instructions.
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2020-12-31 21:51:31 +00:00
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Bind(SixTen(0b010011, 0b0000000000), mcrf);
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Bind(SixTen(0b010011, 0b0000010000), bclrx);
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Bind(SixTen(0b010011, 0b0000100001), crnor);
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Bind(SixTen(0b010011, 0b0000110010), rfi);
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Bind(SixTen(0b010011, 0b0010000001), crandc);
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Bind(SixTen(0b010011, 0b0010010110), isync);
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Bind(SixTen(0b010011, 0b0011000001), crxor);
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Bind(SixTen(0b010011, 0b0011100001), crnand);
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Bind(SixTen(0b010011, 0b0100000001), crand);
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Bind(SixTen(0b010011, 0b0100100001), creqv);
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Bind(SixTen(0b010011, 0b0110100001), crorc);
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Bind(SixTen(0b010011, 0b0111000001), cror);
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Bind(SixTen(0b010011, 0b1000010000), bcctrx);
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Bind(SixTen(0b011111, 0b0000000000), cmp);
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Bind(SixTen(0b011111, 0b0000000100), tw);
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Bind(SixTen(0b011111, 0b0000001000), subfcx); Bind(SixTen(0b011111, 0b1000001000), subfcx);
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Bind(SixTen(0b011111, 0b0000001010), addcx); Bind(SixTen(0b011111, 0b1000001010), addcx);
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2021-01-01 16:46:26 +00:00
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Bind(SixTen(0b011111, 0b0000001011), mulhwux); Bind(SixTen(0b011111, 0b1000001011), mulhwux);
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2020-12-31 21:51:31 +00:00
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Bind(SixTen(0b011111, 0b0000010011), mfcr);
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Bind(SixTen(0b011111, 0b0000010100), lwarx);
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Bind(SixTen(0b011111, 0b0000010111), lwzx);
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Bind(SixTen(0b011111, 0b0000011000), slwx);
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Bind(SixTen(0b011111, 0b0000011010), cntlzwx);
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Bind(SixTen(0b011111, 0b0000011100), andx);
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Bind(SixTen(0b011111, 0b0000100000), cmpl);
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Bind(SixTen(0b011111, 0b0000101000), subfx); Bind(SixTen(0b011111, 0b1000101000), subfx);
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2020-12-31 23:14:38 +00:00
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Bind(SixTen(0b011111, 0b0000110110), dcbst);
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Bind(SixTen(0b011111, 0b0000110111), lwzux);
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Bind(SixTen(0b011111, 0b0000111100), andcx);
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2021-01-01 16:46:26 +00:00
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Bind(SixTen(0b011111, 0b0001001011), mulhwx); Bind(SixTen(0b011111, 0b1001001011), mulhwx);
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2020-12-31 23:14:38 +00:00
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Bind(SixTen(0b011111, 0b0001010011), mfmsr);
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Bind(SixTen(0b011111, 0b0001010110), dcbf);
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Bind(SixTen(0b011111, 0b0001010111), lbzx);
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Bind(SixTen(0b011111, 0b0001101000), negx); Bind(SixTen(0b011111, 0b1001101000), negx);
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Bind(SixTen(0b011111, 0b0001110111), lbzux);
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Bind(SixTen(0b011111, 0b0001111100), norx);
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Bind(SixTen(0b011111, 0b0010001000), subfex); Bind(SixTen(0b011111, 0b1010001000), subfex);
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Bind(SixTen(0b011111, 0b0010001010), addex); Bind(SixTen(0b011111, 0b1010001010), addex);
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Bind(SixTen(0b011111, 0b0010010000), mtcrf);
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Bind(SixTen(0b011111, 0b0010010010), mtmsr);
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Bind(SixTen(0b011111, 0b0010010111), stwx);
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Bind(SixTen(0b011111, 0b0010110111), stwux);
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Bind(SixTen(0b011111, 0b0011001000), subfzex); Bind(SixTen(0b011111, 0b1011001000), subfzex);
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Bind(SixTen(0b011111, 0b0011001010), addzex); Bind(SixTen(0b011111, 0b1011001010), addzex);
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Bind(SixTen(0b011111, 0b0011010111), stbx);
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Bind(SixTen(0b011111, 0b0011101000), subfmex); Bind(SixTen(0b011111, 0b1011101000), subfmex);
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Bind(SixTen(0b011111, 0b0011101010), addmex); Bind(SixTen(0b011111, 0b1011101010), addmex);
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Bind(SixTen(0b011111, 0b0011101011), mullwx); Bind(SixTen(0b011111, 0b1011101011), mullwx);
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Bind(SixTen(0b011111, 0b0011110110), dcbtst);
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Bind(SixTen(0b011111, 0b0011110111), stbux);
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Bind(SixTen(0b011111, 0b0100001010), addx); Bind(SixTen(0b011111, 0b1100001010), addx);
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Bind(SixTen(0b011111, 0b0100010110), dcbt);
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Bind(SixTen(0b011111, 0b0100010111), lhzx);
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Bind(SixTen(0b011111, 0b0100011100), eqvx);
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Bind(SixTen(0b011111, 0b0100110110), eciwx);
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Bind(SixTen(0b011111, 0b0100110111), lhzux);
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Bind(SixTen(0b011111, 0b0100111100), xorx);
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Bind(SixTen(0b011111, 0b0101010111), lhax);
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Bind(SixTen(0b011111, 0b0101110011), mftb);
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Bind(SixTen(0b011111, 0b0101110111), lhaux);
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Bind(SixTen(0b011111, 0b0110010111), sthx);
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Bind(SixTen(0b011111, 0b0110011100), orcx);
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Bind(SixTen(0b011111, 0b0110110110), ecowx);
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Bind(SixTen(0b011111, 0b0110110111), sthux);
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Bind(SixTen(0b011111, 0b0110111100), orx);
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Bind(SixTen(0b011111, 0b0111001011), divwux); Bind(SixTen(0b011111, 0b1111001011), divwux);
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Bind(SixTen(0b011111, 0b0111010110), dcbi);
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2021-01-01 02:12:36 +00:00
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Bind(SixTen(0b011111, 0b0111011100), nandx);
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Bind(SixTen(0b011111, 0b0111101011), divwx); Bind(SixTen(0b011111, 0b1111101011), divwx);
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Bind(SixTen(0b011111, 0b1000000000), mcrxr);
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Bind(SixTen(0b011111, 0b1000010101), lswx);
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Bind(SixTen(0b011111, 0b1000010110), lwbrx);
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Bind(SixTen(0b011111, 0b1000010111), lfsx);
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Bind(SixTen(0b011111, 0b1000011000), srwx);
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Bind(SixTen(0b011111, 0b1000110111), lfsux);
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Bind(SixTen(0b011111, 0b1001010101), lswi);
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Bind(SixTen(0b011111, 0b1001010110), sync);
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Bind(SixTen(0b011111, 0b1001010111), lfdx);
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Bind(SixTen(0b011111, 0b1001110111), lfdux);
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Bind(SixTen(0b011111, 0b1010010101), stswx);
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Bind(SixTen(0b011111, 0b1010010110), stwbrx);
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Bind(SixTen(0b011111, 0b1010010111), stfsx);
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Bind(SixTen(0b011111, 0b1010110111), stfsux);
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Bind(SixTen(0b011111, 0b1011010101), stswi);
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Bind(SixTen(0b011111, 0b1011010111), stfdx);
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Bind(SixTen(0b011111, 0b1011110111), stfdux);
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Bind(SixTen(0b011111, 0b1100010110), lhbrx);
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Bind(SixTen(0b011111, 0b1100011000), srawx);
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Bind(SixTen(0b011111, 0b1100111000), srawix);
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Bind(SixTen(0b011111, 0b1101010110), eieio);
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|
|
Bind(SixTen(0b011111, 0b1110010110), sthbrx);
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|
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|
|
Bind(SixTen(0b011111, 0b1110011010), extshx);
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|
Bind(SixTen(0b011111, 0b1110111010), extsbx);
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Bind(SixTen(0b011111, 0b1111010110), icbi);
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Bind(SixTen(0b011111, 0b1111010111), stfiwx);
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|
Bind(SixTen(0b011111, 0b1111110110), dcbz);
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|
Bind(SixTen(0b111111, 0b0000000000), fcmpu);
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Bind(SixTen(0b111111, 0b0000001100), frspx);
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Bind(SixTen(0b111111, 0b0000001110), fctiwx);
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Bind(SixTen(0b111111, 0b0000001111), fctiwzx);
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|
Bind(SixTen(0b111111, 0b0000100000), fcmpo);
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Bind(SixTen(0b111111, 0b0000100110), mtfsb1x);
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Bind(SixTen(0b111111, 0b0000101000), fnegx);
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Bind(SixTen(0b111111, 0b0001000000), mcrfs);
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Bind(SixTen(0b111111, 0b0001000110), mtfsb0x);
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|
Bind(SixTen(0b111111, 0b0001001000), fmrx);
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|
Bind(SixTen(0b111111, 0b0010000110), mtfsfix);
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|
Bind(SixTen(0b111111, 0b0010001000), fnabsx);
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|
|
Bind(SixTen(0b111111, 0b0100001000), fabsx);
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|
Bind(SixTen(0b111111, 0b1001000111), mffsx);
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|
|
Bind(SixTen(0b111111, 0b1011000111), mtfsfx);
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|
|
|
Bind(SixTen(0b111111, 0b1100101110), fctidx);
|
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|
Bind(SixTen(0b111111, 0b1100101111), fctidzx);
|
|
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|
|
Bind(SixTen(0b111111, 0b1101001110), fcfidx);
|
2020-12-31 23:14:38 +00:00
|
|
|
|
|
|
|
|
Bind(SixTen(0b011111, 0b0101010011), mfspr); // Flagged as "supervisor and user"?
|
|
|
|
|
Bind(SixTen(0b011111, 0b0111010011), mtspr); // Flagged as "supervisor and user"?
|
|
|
|
|
|
|
|
|
|
BindSupervisorConditional(is32bit, SixTen(0b011111, 0b0011010010), mtsr);
|
|
|
|
|
BindSupervisorConditional(is32bit, SixTen(0b011111, 0b0011110010), mtsrin);
|
2021-01-01 02:12:36 +00:00
|
|
|
BindSupervisorConditional(is32bit, SixTen(0b011111, 0b1001010011), mfsr);
|
|
|
|
|
BindSupervisorConditional(is32bit, SixTen(0b011111, 0b1010010011), mfsrin);
|
2020-12-31 23:14:38 +00:00
|
|
|
|
2021-01-01 02:12:36 +00:00
|
|
|
BindSupervisorConditional(is64bit, SixTen(0b011111, 0b0111110010), slbia); // optional
|
|
|
|
|
|
|
|
|
|
// The following are all optional; should I record that?
|
|
|
|
|
BindSupervisor(SixTen(0b011111, 0b0100110010), tlbie);
|
|
|
|
|
BindSupervisor(SixTen(0b011111, 0b0101110010), tlbia);
|
|
|
|
|
BindSupervisor(SixTen(0b011111, 0b1000110110), tlbsync);
|
2020-12-31 21:51:31 +00:00
|
|
|
}
|
2021-01-01 02:12:36 +00:00
|
|
|
|
|
|
|
|
// Third pass: like six-ten except that the top five of the final ten
|
|
|
|
|
// are reserved (i.e. ignored here).
|
|
|
|
|
switch(opcode & SixTen(0b111111, 0b11111)) {
|
|
|
|
|
default: break;
|
|
|
|
|
|
|
|
|
|
Bind(SixTen(0b111011, 0b10010), fdivsx);
|
|
|
|
|
Bind(SixTen(0b111011, 0b10100), fsubsx);
|
|
|
|
|
Bind(SixTen(0b111011, 0b10101), faddsx);
|
|
|
|
|
Bind(SixTen(0b111011, 0b11001), fmulsx);
|
|
|
|
|
Bind(SixTen(0b111011, 0b11100), fmsubsx);
|
|
|
|
|
Bind(SixTen(0b111011, 0b11101), fmaddsx);
|
|
|
|
|
Bind(SixTen(0b111011, 0b11110), fnmsubsx);
|
|
|
|
|
Bind(SixTen(0b111011, 0b11111), fnmaddsx);
|
|
|
|
|
|
|
|
|
|
Bind(SixTen(0b111111, 0b10010), fdivx);
|
|
|
|
|
Bind(SixTen(0b111111, 0b10100), fsubx);
|
|
|
|
|
Bind(SixTen(0b111111, 0b10101), faddx);
|
|
|
|
|
Bind(SixTen(0b111111, 0b11001), fmulx);
|
|
|
|
|
Bind(SixTen(0b111111, 0b11100), fmsubx);
|
|
|
|
|
Bind(SixTen(0b111111, 0b11101), fmaddx);
|
|
|
|
|
Bind(SixTen(0b111111, 0b11110), fnmsubx);
|
|
|
|
|
Bind(SixTen(0b111111, 0b11111), fnmaddx);
|
|
|
|
|
|
|
|
|
|
BindConditional(is64bit, SixTen(0b111011, 0b10110), fsqrtsx);
|
|
|
|
|
BindConditional(is64bit, SixTen(0b111011, 0b11000), fresx);
|
2022-04-09 22:28:51 +00:00
|
|
|
BindConditional(is64bit, SixTen(0b011110, 0b01000), rldclx);
|
|
|
|
|
BindConditional(is64bit, SixTen(0b011110, 0b01001), rldcrx);
|
2021-01-01 02:12:36 +00:00
|
|
|
|
|
|
|
|
// Optional...
|
|
|
|
|
Bind(SixTen(0b111111, 0b10110), fsqrtx);
|
|
|
|
|
Bind(SixTen(0b111111, 0b10111), fselx);
|
|
|
|
|
Bind(SixTen(0b111111, 0b11010), frsqrtex);
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-09 22:28:51 +00:00
|
|
|
// rldicx, rldiclx, rldicrx, rldimix
|
|
|
|
|
if(is64bit(model)) {
|
|
|
|
|
switch(opcode & 0b111111'00000'00000'00000'000000'111'00) {
|
|
|
|
|
default: break;
|
|
|
|
|
case 0b011110'00000'00000'00000'000000'000'00: return instruction<model, validate_reserved_bits, Operation::rldiclx>(opcode);
|
|
|
|
|
case 0b011110'00000'00000'00000'000000'001'00: return instruction<model, validate_reserved_bits, Operation::rldicrx>(opcode);
|
|
|
|
|
case 0b011110'00000'00000'00000'000000'010'00: return instruction<model, validate_reserved_bits, Operation::rldicx>(opcode);
|
|
|
|
|
case 0b011110'00000'00000'00000'000000'011'00: return instruction<model, validate_reserved_bits, Operation::rldimix>(opcode);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-01-01 16:46:26 +00:00
|
|
|
// stwcx. and stdcx.
|
2022-04-02 00:37:36 +00:00
|
|
|
switch(opcode & 0b111111'0000'0000'0000'0000'111111111'1) {
|
2022-04-09 22:28:51 +00:00
|
|
|
default: break;
|
2022-04-05 15:23:54 +00:00
|
|
|
case 0b011111'0000'0000'0000'0000'010010110'1: return instruction<model, validate_reserved_bits, Operation::stwcx_>(opcode);
|
2022-04-02 00:37:36 +00:00
|
|
|
case 0b011111'0000'0000'0000'0000'011010110'1:
|
2022-04-05 15:23:54 +00:00
|
|
|
if(is64bit(model)) return instruction<model, validate_reserved_bits, Operation::stdcx_>(opcode);
|
2021-01-01 16:46:26 +00:00
|
|
|
return Instruction(opcode);
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-09 22:28:51 +00:00
|
|
|
// std, stdu, ld, ldu, lwa
|
|
|
|
|
if(is64bit(model)) {
|
|
|
|
|
switch(opcode & 0b111111'00'00000000'00000000'000000'11) {
|
|
|
|
|
default: break;
|
|
|
|
|
case 0b111010'00'00000000'00000000'000000'00: return instruction<model, validate_reserved_bits, Operation::ld>(opcode);
|
|
|
|
|
case 0b111010'00'00000000'00000000'000000'01: return instruction<model, validate_reserved_bits, Operation::ldu>(opcode);
|
|
|
|
|
case 0b111010'00'00000000'00000000'000000'10: return instruction<model, validate_reserved_bits, Operation::lwa>(opcode);
|
|
|
|
|
case 0b111110'00'00000000'00000000'000000'00: return instruction<model, validate_reserved_bits, Operation::std>(opcode);
|
|
|
|
|
case 0b111110'00'00000000'00000000'000000'01: return instruction<model, validate_reserved_bits, Operation::stdu>(opcode);
|
|
|
|
|
}
|
2021-01-01 16:46:26 +00:00
|
|
|
}
|
2021-01-01 02:12:36 +00:00
|
|
|
|
2021-01-01 16:46:26 +00:00
|
|
|
// sc
|
|
|
|
|
if((opcode & 0b111111'00'00000000'00000000'000000'1'0) == 0b010001'00'00000000'00000000'000000'1'0) {
|
2022-04-05 15:23:54 +00:00
|
|
|
return instruction<model, validate_reserved_bits, Operation::sc>(opcode);
|
2020-12-31 21:51:31 +00:00
|
|
|
}
|
|
|
|
|
|
2020-12-31 21:02:52 +00:00
|
|
|
#undef Six
|
2020-12-31 23:14:38 +00:00
|
|
|
#undef SixTen
|
2020-12-31 21:02:52 +00:00
|
|
|
|
|
|
|
|
#undef Bind
|
|
|
|
|
#undef BindConditional
|
2020-12-31 03:55:59 +00:00
|
|
|
|
2020-12-31 21:02:52 +00:00
|
|
|
return Instruction(opcode);
|
2020-12-31 03:55:59 +00:00
|
|
|
}
|
2022-04-05 15:23:54 +00:00
|
|
|
|
2022-08-10 19:40:46 +00:00
|
|
|
template struct InstructionSet::PowerPC::Decoder<InstructionSet::PowerPC::Model::MPC601, true>;
|
|
|
|
|
template struct InstructionSet::PowerPC::Decoder<InstructionSet::PowerPC::Model::MPC603, true>;
|
|
|
|
|
template struct InstructionSet::PowerPC::Decoder<InstructionSet::PowerPC::Model::MPC620, true>;
|
2022-04-05 15:23:54 +00:00
|
|
|
|
2022-08-10 19:40:46 +00:00
|
|
|
template struct InstructionSet::PowerPC::Decoder<InstructionSet::PowerPC::Model::MPC601, false>;
|
|
|
|
|
template struct InstructionSet::PowerPC::Decoder<InstructionSet::PowerPC::Model::MPC603, false>;
|
|
|
|
|
template struct InstructionSet::PowerPC::Decoder<InstructionSet::PowerPC::Model::MPC620, false>;
|
