6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00
Code Issues Projects Releases Wiki Activity
e650f3772a
CLK/Components/6845/CRTC6845.hpp

511 lines
16 KiB
C++
Raw Normal View History

Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
//
// CRTC6845.hpp
// Clock Signal
//
// Created by Thomas Harte on 31/07/2017.
Removes all instances of the copyright symbol.
2018-05-13 19:19:52 +00:00
// Copyright 2017 Thomas Harte. All rights reserved.
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
//
Switch include guards to `#pragma once`.
2024-01-17 04:34:46 +00:00
#pragma once
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
#include "../../ClockReceiver/ClockReceiver.hpp"
#include <cstdint>
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
2017-08-01 00:14:46 +00:00
#include <cstdio>
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
Simplify namespace syntax.
2023-05-10 21:02:18 +00:00
namespace Motorola::CRTC {
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
2017-08-01 00:14:46 +00:00
struct BusState {
Ensures full 6845 instance state initialisation and uses an unsigned shifter.
2017-10-18 02:10:28 +00:00
bool display_enable = false;
bool hsync = false;
bool vsync = false;
bool cursor = false;
uint16_t refresh_address = 0;
uint16_t row_address = 0;
Implement blinking text.
2023-12-05 03:02:38 +00:00
// Not strictly part of the bus state; provided because the partition between 6845 and bus handler
// doesn't quite hold up in some emulated systems where the two are integrated and share more state.
int field_count = 0;
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
2017-08-01 00:14:46 +00:00
};
Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
2017-08-01 20:15:19 +00:00
class BusHandler {
public:
Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
2017-08-26 17:56:23 +00:00
/*!
Performs the first phase of a 6845 bus cycle; this is the phase in which it is intended that
systems using the 6845 respect the bus state and produce pixels, sync or whatever they require.
*/
void perform_bus_cycle_phase1(const BusState &) {}
/*!
Eliminates all emdashes in cross-platform code.
2018-05-13 19:34:31 +00:00
Performs the second phase of a 6845 bus cycle. Some bus state, including sync, is updated
Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
2017-08-26 17:56:23 +00:00
directly after phase 1 and hence is visible to an observer during phase 2. Handlers may therefore
implement @c perform_bus_cycle_phase2 to be notified of the availability of that state without
having to wait until the next cycle has begun.
*/
void perform_bus_cycle_phase2(const BusState &) {}
Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
2017-08-01 20:15:19 +00:00
};
Move personality into type.
2023-12-27 21:15:52 +00:00
enum class Personality {
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 22:10:07 +00:00
HD6845S, // Type 0 in CPC parlance. Zero-width HSYNC available, no status, programmable VSYNC length.
Adds an initial implementation of display skew, as a completely live property.
2017-08-30 02:16:40 +00:00
// Considered exactly identical to the UM6845, so this enum covers both.
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 22:10:07 +00:00
UM6845R, // Type 1 in CPC parlance. Status register, fixed-length VSYNC.
MC6845, // Type 2. No status register, fixed-length VSYNC, no zero-length HSYNC.
Move personality into type.
2023-12-27 21:15:52 +00:00
AMS40226, // Type 3. Status is get register, fixed-length VSYNC, no zero-length HSYNC.
EGA, // Extended EGA-style CRTC; uses 16-bit addressing throughout.
Forced users of the 6845 to be explicit about which type. So far with no effect.
2017-08-10 16:28:57 +00:00
};
Begin process of meaningful naming. This is in part for readability, but primarily because the differences in VGA/EGA register definitions are better handled at set rather than during execution.
2024-01-08 20:35:44 +00:00
constexpr bool is_egavga(Personality p) {
return p >= Personality::EGA;
}
Add a cursor-type template parameter.
2023-12-04 14:45:32 +00:00
// https://www.pcjs.org/blog/2018/03/20/ advises that "the behavior of bits 5 and 6 [of register 10, the cursor start
// register is really card specific".
//
// This enum captures those specifics.
Move personality into type.
2023-12-27 21:15:52 +00:00
enum class CursorType {
Add a cursor-type template parameter.
2023-12-04 14:45:32 +00:00
/// No cursor signal is generated.
None,
/// MDA style: 00 => symmetric blinking; 01 or 10 => no blinking; 11 => short on, long off.
MDA,
/// EGA style: ignore the bits completely.
EGA,
};
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 22:10:07 +00:00
// TODO UM6845R and R12/R13; see http://www.cpcwiki.eu/index.php/CRTC#CRTC_Differences
Move personality into type.
2023-12-27 21:15:52 +00:00
template <class BusHandlerT, Personality personality, CursorType cursor_type> class CRTC6845 {
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
public:
Move personality into type.
2023-12-27 21:15:52 +00:00
CRTC6845(BusHandlerT &bus_handler) noexcept :
bus_handler_(bus_handler), status_(0) {}
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
2017-08-01 00:14:46 +00:00
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-23 01:54:48 +00:00
void select_register(uint8_t r) {
selected_register_ = r;
}
Removes const from get_status and get_register, as both may now logically mutate the object.
2017-08-27 22:13:55 +00:00
uint8_t get_status() {
Move personality into type.
2023-12-27 21:15:52 +00:00
switch(personality) {
case Personality::UM6845R: return status_ | (bus_state_.vsync ? 0x20 : 0x00);
case Personality::AMS40226: return get_register();
Adjust indentation.
2024-01-02 03:45:11 +00:00
default: return 0xff;
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 22:10:07 +00:00
}
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-23 01:54:48 +00:00
return 0xff;
}
Removes const from get_status and get_register, as both may now logically mutate the object.
2017-08-27 22:13:55 +00:00
uint8_t get_register() {
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 22:10:07 +00:00
if(selected_register_ == 31) status_ &= ~0x80;
if(selected_register_ == 16 || selected_register_ == 17) status_ &= ~0x40;
Move personality into type.
2023-12-27 21:15:52 +00:00
if(personality == Personality::UM6845R && selected_register_ == 31) return dummy_register_;
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-23 01:54:48 +00:00
if(selected_register_ < 12 || selected_register_ > 17) return 0xff;
return registers_[selected_register_];
}
void set_register(uint8_t value) {
Introduce some vertical metrics.
2024-01-09 02:49:24 +00:00
static constexpr bool is_ega = is_egavga(personality);
Switch to named values for everything except blink mode.
2024-01-10 03:03:24 +00:00
auto load_low = [value](uint16_t &target) {
target = (target & 0xff00) | value;
};
auto load_high = [value](uint16_t &target) {
constexpr uint8_t mask = RefreshMask >> 8;
target = uint16_t((target & 0x00ff) | ((value & mask) << 8));
};
Begin process of meaningful naming. This is in part for readability, but primarily because the differences in VGA/EGA register definitions are better handled at set rather than during execution.
2024-01-08 20:35:44 +00:00
switch(selected_register_) {
case 0: layout_.horizontal.total = value; break;
case 1: layout_.horizontal.displayed = value; break;
Subsume vertical sync position.
2024-01-09 03:28:46 +00:00
case 2: layout_.horizontal.start_sync = value; break;
Introduce some vertical metrics.
2024-01-09 02:49:24 +00:00
case 3:
Remove non-functional EGA switches.
2024-01-12 03:00:48 +00:00
layout_.horizontal.sync_width = value & 0xf;
layout_.vertical.sync_lines = value >> 4;
// TODO: vertical sync lines:
// "(0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)"
Introduce some vertical metrics.
2024-01-09 02:49:24 +00:00
break;
Remove non-functional EGA switches.
2024-01-12 03:00:48 +00:00
case 4: layout_.vertical.total = value & 0x7f; break;
Subsume vertical sync position.
2024-01-09 03:28:46 +00:00
case 5: layout_.vertical.adjust = value & 0x1f; break;
case 6: layout_.vertical.displayed = value & 0x7f; break;
case 7: layout_.vertical.start_sync = value & 0x7f; break;
Switch to named values for everything except blink mode.
2024-01-10 03:03:24 +00:00
case 8:
switch(value & 3) {
default: layout_.interlace_mode_ = InterlaceMode::Off; break;
case 0b01: layout_.interlace_mode_ = InterlaceMode::InterlaceSync; break;
case 0b11: layout_.interlace_mode_ = InterlaceMode::InterlaceSyncAndVideo; break;
}
Grab cursor type.
2024-01-11 20:10:43 +00:00
// Per CPC documentation, skew doesn't work on a "type 1 or 2", i.e. an MC6845 or a UM6845R.
if(personality != Personality::UM6845R && personality != Personality::MC6845) {
switch((value >> 4)&3) {
default: display_skew_mask_ = 1; break;
case 1: display_skew_mask_ = 2; break;
case 2: display_skew_mask_ = 4; break;
}
}
Switch to named values for everything except blink mode.
2024-01-10 03:03:24 +00:00
break;
case 9: layout_.vertical.end_row = value & 0x1f; break;
case 10:
layout_.vertical.start_cursor = value & 0x1f;
Grab cursor type.
2024-01-11 20:10:43 +00:00
layout_.cursor_flags = (value >> 5) & 3;
Switch to named values for everything except blink mode.
2024-01-10 03:03:24 +00:00
break;
case 11:
layout_.vertical.end_cursor = value & 0x1f;
break;
case 12: load_high(layout_.start_address); break;
case 13: load_low(layout_.start_address); break;
case 14: load_high(layout_.cursor_address); break;
case 15: load_low(layout_.cursor_address); break;
Begin process of meaningful naming. This is in part for readability, but primarily because the differences in VGA/EGA register definitions are better handled at set rather than during execution.
2024-01-08 20:35:44 +00:00
}
Switch interpretation to support cursor on/off.
2023-12-04 20:54:56 +00:00
static constexpr uint8_t masks[] = {
Begin process of meaningful naming. This is in part for readability, but primarily because the differences in VGA/EGA register definitions are better handled at set rather than during execution.
2024-01-08 20:35:44 +00:00
0xff, // Horizontal total.
0xff, // Horizontal display end.
0xff, // Start horizontal blank.
0xff, //
// EGA: b0–b4: end of horizontal blank;
// b5–b6: "Number of character clocks to delay start of display after Horizontal Total has been reached."
is_ega ? 0xff : 0x7f, // Start horizontal retrace.
0x1f, 0x7f, 0x7f,
Extend refresh address to 16-bit in 'EGA' mode.
2023-12-27 21:17:25 +00:00
0xff, 0x1f, 0x7f, 0x1f,
uint8_t(RefreshMask >> 8), uint8_t(RefreshMask),
uint8_t(RefreshMask >> 8), uint8_t(RefreshMask),
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-23 01:54:48 +00:00
};
Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
2017-08-26 21:54:54 +00:00
if(selected_register_ < 16) {
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-23 01:54:48 +00:00
registers_[selected_register_] = value & masks[selected_register_];
Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
2017-08-26 21:54:54 +00:00
}
Move personality into type.
2023-12-27 21:15:52 +00:00
if(selected_register_ == 31 && personality == Personality::UM6845R) {
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 22:10:07 +00:00
dummy_register_ = value;
}
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-23 01:54:48 +00:00
}
void trigger_light_pen() {
registers_[17] = bus_state_.refresh_address & 0xff;
registers_[16] = bus_state_.refresh_address >> 8;
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 22:10:07 +00:00
status_ |= 0x40;
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-23 01:54:48 +00:00
}
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
bool eof_latched_ = false;
Attempt to skirt with coherence.
2024-09-30 03:08:39 +00:00
bool eom_latched_ = false;
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
bool extra_scanline_ = false;
uint16_t next_row_address_ = 0;
Attempt to skirt with coherence.
2024-09-30 03:08:39 +00:00
bool adjustment_in_progress_ = false;
Take a swing at vertical sync.
2024-09-28 01:14:57 +00:00
bool odd_field_ = false;
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
void run_for(Cycles cycles) {
Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.
2019-10-30 02:36:29 +00:00
auto cyles_remaining = cycles.as_integral();
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
2017-08-01 00:14:46 +00:00
while(cyles_remaining--) {
Restore some form of visuals.
2024-09-27 02:08:22 +00:00
// Intention of code below: all conditionals are evaluated as if functional; they should be
// ordered so that whatever assignments result don't affect any subsequent conditionals
// Do bus work.
// bus_state_.cursor = is_cursor_line_ &&
// bus_state_.refresh_address == layout_.cursor_address;
Limit vertical visibility.
2024-09-30 17:35:28 +00:00
bus_state_.display_enable = character_is_visible_ && line_is_visible_;
Restore some form of visuals.
2024-09-27 02:08:22 +00:00
// TODO: considate the two below.
perform_bus_cycle_phase1();
perform_bus_cycle_phase2();
//
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
const bool character_total_hit = character_counter_ == layout_.horizontal.total;
Restore some form of visuals.
2024-09-27 02:08:22 +00:00
const uint8_t lines_per_row = layout_.interlace_mode_ == InterlaceMode::InterlaceSyncAndVideo ? layout_.vertical.end_row & ~1 : layout_.vertical.end_row;
Attempt to skirt with coherence.
2024-09-30 03:08:39 +00:00
const bool row_end_hit = bus_state_.row_address == lines_per_row && !adjustment_in_progress_;
Restore some form of visuals.
2024-09-27 02:08:22 +00:00
const bool new_frame =
character_total_hit && eof_latched_ &&
(
layout_.interlace_mode_ == InterlaceMode::Off ||
!(bus_state_.field_count&1) ||
extra_scanline_
);
Made a quick attempt at properly updating the refresh address.
2017-08-01 11:36:03 +00:00
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
//
// Horizontal.
//
// Update horizontal sync.
if(bus_state_.hsync) {
++hsync_counter_;
bus_state_.hsync = hsync_counter_ != layout_.horizontal.sync_width;
}
if(character_counter_ == layout_.horizontal.start_sync) {
hsync_counter_ = 0;
bus_state_.hsync = true;
}
Restore some form of visuals.
2024-09-27 02:08:22 +00:00
// Check for end-of-line.
if(character_total_hit) {
character_counter_ = 0;
character_is_visible_ = true;
} else {
character_counter_++;
}
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
Fix accidental skew, off-by-one end of line.
2024-09-30 17:20:18 +00:00
// Check for end of visible characters.
if(character_counter_ == layout_.horizontal.displayed) {
character_is_visible_ = false;
}
Stabilise image, albeit incorrectly.
2024-09-30 17:16:03 +00:00
//
// End-of-frame.
//
if(new_frame) {
eom_latched_ = eof_latched_ = false;
} else {
eom_latched_ |= character_counter_ == 1 && row_end_hit && row_counter_ == layout_.vertical.total;
eof_latched_ |= character_counter_ == 2 && eom_latched_ && !adjustment_in_progress_;
}
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
//
// Vertical.
//
Attempt to skirt with coherence.
2024-09-30 03:08:39 +00:00
if(character_total_hit) {
if(eof_latched_ ) {
bus_state_.row_address = 0;
eof_latched_ = eom_latched_ = false;
} else if(row_end_hit) {
bus_state_.row_address = 0;
} else if(layout_.interlace_mode_ == InterlaceMode::InterlaceSyncAndVideo) {
bus_state_.row_address = (bus_state_.row_address + 2) & ~1 & 31;
} else {
bus_state_.row_address = (bus_state_.row_address + 1) & 31;
}
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 22:10:07 +00:00
}
Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.
2017-08-26 21:22:48 +00:00
Stabilise image, albeit incorrectly.
2024-09-30 17:16:03 +00:00
row_counter_ = next_row_counter_;
if(new_frame) {
next_row_counter_ = 0;
Limit vertical visibility.
2024-09-30 17:35:28 +00:00
is_first_scanline_ = true;
Stabilise image, albeit incorrectly.
2024-09-30 17:16:03 +00:00
} else {
next_row_counter_ = row_end_hit && character_total_hit ? (next_row_counter_ + 1) : next_row_counter_;
Limit vertical visibility.
2024-09-30 17:35:28 +00:00
is_first_scanline_ &= !row_end_hit;
Stabilise image, albeit incorrectly.
2024-09-30 17:16:03 +00:00
}
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
Take a swing at vertical sync.
2024-09-28 01:14:57 +00:00
// Sync.
const bool vsync_horizontal =
(!odd_field_ && !character_counter_) ||
(odd_field_ && character_counter_ == (layout_.horizontal.total >> 1));
if(vsync_horizontal) {
Attempt to skirt with coherence.
2024-09-30 03:08:39 +00:00
if(row_counter_ == layout_.vertical.start_sync || bus_state_.vsync) {
Take a swing at vertical sync.
2024-09-28 01:14:57 +00:00
bus_state_.vsync = true;
vsync_counter_ = (vsync_counter_ + 1) & 0xf;
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
} else {
Take a swing at vertical sync.
2024-09-28 01:14:57 +00:00
vsync_counter_ = 0;
}
if(vsync_counter_ == layout_.vertical.sync_lines) {
bus_state_.vsync = false;
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
}
}
Limit vertical visibility.
2024-09-30 17:35:28 +00:00
if(is_first_scanline_) {
line_is_visible_ = true;
} else if(line_is_visible_ && row_counter_ == layout_.vertical.displayed) {
line_is_visible_ = false;
// ++field_counter_;
}
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
//
// Addressing.
//
Make negligible progress.
2024-09-25 23:30:08 +00:00
if(new_frame) {
bus_state_.refresh_address = layout_.start_address;
} else if(character_total_hit) {
Improve address counting.
2024-09-28 01:27:56 +00:00
bus_state_.refresh_address = line_address_;
Make negligible progress.
2024-09-25 23:30:08 +00:00
} else {
Improve address counting.
2024-09-28 01:27:56 +00:00
bus_state_.refresh_address = (bus_state_.refresh_address + 1) & RefreshMask;
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
}
Fix accidental skew, off-by-one end of line.
2024-09-30 17:20:18 +00:00
if(new_frame) {
line_address_ = layout_.start_address;
} else if(character_counter_ == layout_.horizontal.displayed && row_end_hit) {
line_address_ = bus_state_.refresh_address;
}
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
2017-08-01 00:14:46 +00:00
}
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
}
Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
2017-08-26 16:59:59 +00:00
const BusState &get_bus_state() const {
return bus_state_;
}
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-23 01:54:48 +00:00
private:
Extend refresh address to 16-bit in 'EGA' mode.
2023-12-27 21:17:25 +00:00
static constexpr uint16_t RefreshMask = (personality >= Personality::EGA) ? 0xffff : 0x3fff;
Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
2017-08-26 17:56:23 +00:00
inline void perform_bus_cycle_phase1() {
Adds an initial implementation of display skew, as a completely live property.
2017-08-30 02:16:40 +00:00
// Skew theory of operation: keep a history of the last three states, and apply whichever is selected.
Restore some form of visuals.
2024-09-27 02:08:22 +00:00
// character_is_visible_shifter_ = (character_is_visible_shifter_ << 1) | unsigned(character_is_visible_);
// bus_state_.display_enable = (int(character_is_visible_shifter_) & display_skew_mask_) && line_is_visible_;
Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
2017-08-26 17:56:23 +00:00
bus_handler_.perform_bus_cycle_phase1(bus_state_);
}
inline void perform_bus_cycle_phase2() {
bus_handler_.perform_bus_cycle_phase2(bus_state_);
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
}
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
// inline void do_end_of_line() {
// if constexpr (cursor_type != CursorType::None) {
// // Check for cursor disable.
// // TODO: this is handled differently on the EGA, should I ever implement that.
// is_cursor_line_ &= bus_state_.row_address != layout_.vertical.end_cursor;
// }
//
// // Check for end of vertical sync.
// if(bus_state_.vsync) {
// vsync_counter_ = (vsync_counter_ + 1) & 15;
// // On the UM6845R and AMS40226, honour the programmed vertical sync time; on the other CRTCs
// // always use a vertical sync count of 16.
// switch(personality) {
// case Personality::HD6845S:
// case Personality::AMS40226:
// bus_state_.vsync = vsync_counter_ != layout_.vertical.sync_lines;
// break;
// default:
// bus_state_.vsync = vsync_counter_ != 0;
// break;
// }
// }
//
// if(is_in_adjustment_period_) {
// line_counter_++;
// if(line_counter_ == layout_.vertical.adjust) {
// is_in_adjustment_period_ = false;
// do_end_of_frame();
// }
// } else {
// // Advance vertical counter.
// if(bus_state_.row_address == layout_.end_row()) {
// bus_state_.row_address = 0;
// line_address_ = end_of_line_address_;
//
// // Check for entry into the overflow area.
// if(line_counter_ == layout_.vertical.total) {
// if(layout_.vertical.adjust) {
// line_counter_ = 0;
// is_in_adjustment_period_ = true;
// } else {
// do_end_of_frame();
// }
// } else {
// line_counter_ = (line_counter_ + 1) & 0x7f;
// }
//
// // Check for start of vertical sync.
// if(line_counter_ == layout_.vertical.start_sync) {
// bus_state_.vsync = true;
// vsync_counter_ = 0;
// }
//
// // Check for end of visible lines.
// if(line_counter_ == layout_.vertical.displayed) {
// line_is_visible_ = false;
// }
// } else {
// bus_state_.row_address = (bus_state_.row_address + 1) & 0x1f;
// }
// }
//
// bus_state_.refresh_address = line_address_;
// character_counter_ = 0;
// character_is_visible_ = (layout_.horizontal.displayed != 0);
//
// if constexpr (cursor_type != CursorType::None) {
// // Check for cursor enable.
// is_cursor_line_ |= bus_state_.row_address == layout_.vertical.start_cursor;
//
// switch(cursor_type) {
// // MDA-style blinking.
// // https://retrocomputing.stackexchange.com/questions/27803/what-are-the-blinking-rates-of-the-caret-and-of-blinking-text-on-pc-graphics-car
// // gives an 8/8 pattern for regular blinking though mode 11 is then just a guess.
// case CursorType::MDA:
// switch(layout_.cursor_flags) {
// case 0b11: is_cursor_line_ &= (bus_state_.field_count & 8) < 3; break;
// case 0b00: is_cursor_line_ &= bool(bus_state_.field_count & 8); break;
// case 0b01: is_cursor_line_ = false; break;
// case 0b10: is_cursor_line_ = true; break;
// default: break;
// }
// break;
// }
// }
// }
//
// inline void do_end_of_frame() {
// line_counter_ = 0;
// line_is_visible_ = true;
// line_address_ = layout_.start_address;
// bus_state_.refresh_address = line_address_;
// ++bus_state_.field_count;
// }
Factored out the stuff of stuffing the bus.
2017-08-14 16:42:22 +00:00
Move personality into type.
2023-12-27 21:15:52 +00:00
BusHandlerT &bus_handler_;
Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
2017-08-01 00:14:46 +00:00
BusState bus_state_;
Switch to named values for everything except blink mode.
2024-01-10 03:03:24 +00:00
enum class InterlaceMode {
Off,
InterlaceSync,
InterlaceSyncAndVideo,
};
enum class BlinkMode {
// TODO.
};
Begin process of meaningful naming. This is in part for readability, but primarily because the differences in VGA/EGA register definitions are better handled at set rather than during execution.
2024-01-08 20:35:44 +00:00
struct {
struct {
uint8_t total;
uint8_t displayed;
Subsume vertical sync position.
2024-01-09 03:28:46 +00:00
uint8_t start_sync;
Introduce some vertical metrics.
2024-01-09 02:49:24 +00:00
uint8_t sync_width;
Begin process of meaningful naming. This is in part for readability, but primarily because the differences in VGA/EGA register definitions are better handled at set rather than during execution.
2024-01-08 20:35:44 +00:00
} horizontal;
Introduce some vertical metrics.
2024-01-09 02:49:24 +00:00
struct {
uint8_t total;
uint8_t displayed;
Subsume vertical sync position.
2024-01-09 03:28:46 +00:00
uint8_t start_sync;
Introduce some vertical metrics.
2024-01-09 02:49:24 +00:00
uint8_t sync_lines;
uint8_t adjust;
Switch to named values for everything except blink mode.
2024-01-10 03:03:24 +00:00
uint8_t end_row;
uint8_t start_cursor;
uint8_t end_cursor;
Introduce some vertical metrics.
2024-01-09 02:49:24 +00:00
} vertical;
Switch to named values for everything except blink mode.
2024-01-10 03:03:24 +00:00
InterlaceMode interlace_mode_ = InterlaceMode::Off;
Begin CRTC rejig.
2024-09-24 01:11:54 +00:00
uint8_t end_row() const {
return interlace_mode_ == InterlaceMode::InterlaceSyncAndVideo ? vertical.end_row & ~1 : vertical.end_row;
}
Switch to named values for everything except blink mode.
2024-01-10 03:03:24 +00:00
uint16_t start_address;
uint16_t cursor_address;
uint16_t light_pen_address;
Grab cursor type.
2024-01-11 20:10:43 +00:00
uint8_t cursor_flags;
Begin process of meaningful naming. This is in part for readability, but primarily because the differences in VGA/EGA register definitions are better handled at set rather than during execution.
2024-01-08 20:35:44 +00:00
} layout_;
uint8_t registers_[18]{};
Ensures full 6845 instance state initialisation and uses an unsigned shifter.
2017-10-18 02:10:28 +00:00
uint8_t dummy_register_ = 0;
int selected_register_ = 0;
I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
2017-08-01 02:01:54 +00:00
Ensures full 6845 instance state initialisation and uses an unsigned shifter.
2017-10-18 02:10:28 +00:00
uint8_t character_counter_ = 0;
Stabilise image, albeit incorrectly.
2024-09-30 17:16:03 +00:00
uint8_t row_counter_ = 0, next_row_counter_ = 0;;
I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
2017-08-01 02:01:54 +00:00
Limit vertical visibility.
2024-09-30 17:35:28 +00:00
bool character_is_visible_ = false, line_is_visible_ = false, is_first_scanline_ = false;
I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
2017-08-01 02:01:54 +00:00
Ensures full 6845 instance state initialisation and uses an unsigned shifter.
2017-10-18 02:10:28 +00:00
int hsync_counter_ = 0;
int vsync_counter_ = 0;
bool is_in_adjustment_period_ = false;
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-23 01:54:48 +00:00
Ensures full 6845 instance state initialisation and uses an unsigned shifter.
2017-10-18 02:10:28 +00:00
uint16_t line_address_ = 0;
uint16_t end_of_line_address_ = 0;
uint8_t status_ = 0;
Adds an initial implementation of display skew, as a completely live property.
2017-08-30 02:16:40 +00:00
int display_skew_mask_ = 1;
Ensures full 6845 instance state initialisation and uses an unsigned shifter.
2017-10-18 02:10:28 +00:00
unsigned int character_is_visible_shifter_ = 0;
Enable the cursor signal; no blink action yet.
2023-12-03 22:57:19 +00:00
bool is_cursor_line_ = false;
Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
2017-07-31 23:56:59 +00:00
};
}
Reference in New Issue Copy Permalink