2024-02-17 02:35:49 +00:00
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//
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// Operation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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namespace InstructionSet::ARM {
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enum class Operation {
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2024-02-18 03:13:51 +00:00
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/// Rd = Op1 AND Op2.
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AND,
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/// Rd = Op1 EOR Op2.
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EOR,
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/// Rd = Op1 - Op2.
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SUB,
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/// Rd = Op2 - Op1.
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RSB,
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/// Rd = Op1 + Op2.
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ADD,
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/// Rd = Op1 + Ord2 + C.
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ADC,
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/// Rd = Op1 - Op2 + C.
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SBC,
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/// Rd = Op2 - Op1 + C.
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RSC,
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/// Set condition codes on Op1 AND Op2.
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TST,
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/// Set condition codes on Op1 EOR Op2.
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TEQ,
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/// Set condition codes on Op1 - Op2.
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CMP,
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/// Set condition codes on Op1 + Op2.
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CMN,
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/// Rd = Op1 OR Op2.
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ORR,
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/// Rd = Op2
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MOV,
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/// Rd = Op1 AND NOT Op2.
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BIC,
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/// Rd = NOT Op2.
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MVN,
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2024-02-17 02:35:49 +00:00
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2024-02-21 19:17:01 +00:00
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MUL, MLA,
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2024-02-17 20:41:57 +00:00
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B, BL,
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2024-02-17 02:35:49 +00:00
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2024-02-18 03:13:51 +00:00
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LDR, STR,
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LDM, STM,
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2024-02-21 20:25:57 +00:00
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SWI,
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2024-02-17 02:35:49 +00:00
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2024-02-21 20:25:57 +00:00
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CDP,
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MRC, MCR,
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2024-02-17 02:35:49 +00:00
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CoprocessorDataTransfer,
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Undefined,
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};
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enum class Condition {
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EQ, NE, CS, CC,
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MI, PL, VS, VC,
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HI, LS, GE, LT,
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GT, LE, AL, NV,
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};
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}
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