From ba042610af7f9579845303eca4c36b7bf8daffeb Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 6 Apr 2026 12:24:48 -0400 Subject: [PATCH 1/2] Add missing header, adjust LEAx timing. --- Processors/6809/Perform.hpp | 8 ++++---- Processors/6809/Registers.hpp | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/Processors/6809/Perform.hpp b/Processors/6809/Perform.hpp index 77cc86d87..9da85153e 100644 --- a/Processors/6809/Perform.hpp +++ b/Processors/6809/Perform.hpp @@ -545,10 +545,10 @@ Cycles perform( case STY: st(registers, word); return 0; case STS: st(registers, word); return 0; - case LEAU: lea(registers, word); return 0; - case LEAX: lea(registers, word); return 0; - case LEAY: lea(registers, word); return 0; - case LEAS: lea(registers, word); return 0; + case LEAU: lea(registers, word); return 1; + case LEAX: lea(registers, word); return 1; + case LEAY: lea(registers, word); return 1; + case LEAS: lea(registers, word); return 1; case MUL: mul(registers); return 9; // Per 6809cyc.txt; might need more research. diff --git a/Processors/6809/Registers.hpp b/Processors/6809/Registers.hpp index 8dcf75180..470e06f04 100644 --- a/Processors/6809/Registers.hpp +++ b/Processors/6809/Registers.hpp @@ -9,6 +9,7 @@ #pragma once #include +#include #include #include "Numeric/RegisterSizes.hpp" From 116ed6f497789be950e6efcc6cfb6d85699775e4 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 6 Apr 2026 14:32:59 -0400 Subject: [PATCH 2/2] Correct LEAx length, and hence normalise CD90-640 disk RPM. --- Machines/Thomson/MO5/CD90-640.cpp | 5 +-- OSBindings/Mac/Clock SignalTests/6809Tests.mm | 41 ++++++++++--------- Processors/6809/6809.hpp | 6 +-- Processors/6809/Perform.hpp | 3 +- 4 files changed, 26 insertions(+), 29 deletions(-) diff --git a/Machines/Thomson/MO5/CD90-640.cpp b/Machines/Thomson/MO5/CD90-640.cpp index f3e5cc3a8..174660555 100644 --- a/Machines/Thomson/MO5/CD90-640.cpp +++ b/Machines/Thomson/MO5/CD90-640.cpp @@ -11,10 +11,7 @@ using namespace Thomson; CD90_640::CD90_640() : WD::WD1770(P1770) { - // 325 is a peculiar RPM, but seems to match a spin-up test in the disk ROM that polls the WD1770's status register - // index hole bit and counts time. Furthermore there are other machines with unusual RPMs. Could definitely - // still just imply an issue elsewhere in the emulator though. - emplace_drives(2, 8000000, 325, 2); + emplace_drives(2, 8'000'000, 300, 2); } uint8_t CD90_640::control() { diff --git a/OSBindings/Mac/Clock SignalTests/6809Tests.mm b/OSBindings/Mac/Clock SignalTests/6809Tests.mm index f3a4ff8be..be2514c89 100644 --- a/OSBindings/Mac/Clock SignalTests/6809Tests.mm +++ b/OSBindings/Mac/Clock SignalTests/6809Tests.mm @@ -824,7 +824,8 @@ struct M6809Traits { sequence(0xbf); // STY } - // Omitted entirely: LEAS, LEAU, LEAX, LEAY that come only in indexed mode. Maybe use those as the indexed test? + // Omitted entirely: LEAS, LEAU, LEAX, LEAY that come only in indexed mode. LEAS is the subject of the indexed + // timing tests, and I _assume_ the rest conform. // MARK: - JMP @@ -1087,35 +1088,35 @@ struct M6809Traits { test( {0x32, NoOffset | RegX}, // ,R { - RW::Read, RW::Read, RW::NoData + RW::Read, RW::Read, RW::NoData, RW::NoData, } ); test( {0x32, NoOffset | RegX | Indirect}, // [,R] { - RW::Read, RW::Read, RW::NoData, RW::Read, RW::Read, RW::NoData + RW::Read, RW::Read, RW::NoData, RW::Read, RW::Read, RW::NoData, RW::NoData, } ); test( {0x32, Offset5bit | RegX}, // [5n,R] { - RW::Read, RW::Read, RW::NoData, RW::NoData + RW::Read, RW::Read, RW::NoData, RW::NoData, RW::NoData, } ); test( {0x32, Offset8bit | RegX, 0x00}, // 8n,R { - RW::Read, RW::Read, RW::Read, RW::NoData + RW::Read, RW::Read, RW::Read, RW::NoData, RW::NoData, } ); test( {0x32, Offset8bit | RegX | Indirect, 0x00}, // [8n,R] { - RW::Read, RW::Read, RW::Read, RW::NoData, RW::Read, RW::Read, RW::NoData, + RW::Read, RW::Read, RW::Read, RW::NoData, RW::Read, RW::Read, RW::NoData, RW::NoData, } ); @@ -1124,7 +1125,7 @@ struct M6809Traits { { RW::Read, RW::Read, RW::Read, RW::Read, - RW::NoData, RW::NoData, RW::NoData, + RW::NoData, RW::NoData, RW::NoData, RW::NoData, } ); @@ -1132,7 +1133,7 @@ struct M6809Traits { {0x32, ARegisterOffset | RegX}, // A,R { RW::Read, RW::Read, - RW::NoData, RW::NoData, + RW::NoData, RW::NoData, RW::NoData, } ); @@ -1141,7 +1142,7 @@ struct M6809Traits { { RW::Read, RW::Read, RW::NoData, RW::NoData, - RW::Read, RW::Read, RW::NoData, + RW::Read, RW::Read, RW::NoData, RW::NoData, } ); @@ -1152,7 +1153,7 @@ struct M6809Traits { {0x32, DRegisterOffset | RegX}, // D,R { RW::Read, RW::Read, - RW::NoData, RW::NoData, RW::NoData, RW::NoData, RW::NoData, + RW::NoData, RW::NoData, RW::NoData, RW::NoData, RW::NoData, RW::NoData, } ); @@ -1161,7 +1162,7 @@ struct M6809Traits { { RW::Read, RW::Read, RW::NoData, RW::NoData, RW::NoData, RW::NoData, RW::NoData, - RW::Read, RW::Read, RW::NoData, + RW::Read, RW::Read, RW::NoData, RW::NoData, } ); @@ -1169,7 +1170,7 @@ struct M6809Traits { {0x32, PostInc1 | RegX}, // R+ { RW::Read, RW::Read, - RW::NoData, RW::NoData, RW::NoData, + RW::NoData, RW::NoData, RW::NoData, RW::NoData, } ); @@ -1177,7 +1178,7 @@ struct M6809Traits { {0x32, PreDec1 | RegX}, // -R { RW::Read, RW::Read, - RW::NoData, RW::NoData, RW::NoData, + RW::NoData, RW::NoData, RW::NoData, RW::NoData, } ); @@ -1185,7 +1186,7 @@ struct M6809Traits { {0x32, PostInc2 | RegX}, // R++ { RW::Read, RW::Read, - RW::NoData, RW::NoData, RW::NoData, RW::NoData, + RW::NoData, RW::NoData, RW::NoData, RW::NoData, RW::NoData, } ); @@ -1194,14 +1195,14 @@ struct M6809Traits { { RW::Read, RW::Read, RW::NoData, RW::NoData, RW::NoData, RW::NoData, - RW::Read, RW::Read, RW::NoData, + RW::Read, RW::Read, RW::NoData, RW::NoData, } ); test( {0x32, PCOffset8bit | RegX, 0x00}, // 8n, PC { - RW::Read, RW::Read, RW::Read, RW::NoData, + RW::Read, RW::Read, RW::Read, RW::NoData, RW::NoData, } ); @@ -1209,7 +1210,7 @@ struct M6809Traits { {0x32, PCOffset8bit | RegX | Indirect, 0x00, 0x00, 0x00}, // [8n, PC] { RW::Read, RW::Read, RW::Read, RW::NoData, - RW::Read, RW::Read, RW::NoData, + RW::Read, RW::Read, RW::NoData, RW::NoData, } ); @@ -1217,7 +1218,7 @@ struct M6809Traits { {0x32, PCOffset16bit | RegX, 0x00, 0x00}, // 16n, PC { RW::Read, RW::Read, RW::Read, RW::Read, - RW::NoData, RW::NoData, RW::NoData, RW::NoData, + RW::NoData, RW::NoData, RW::NoData, RW::NoData, RW::NoData, } ); @@ -1226,7 +1227,7 @@ struct M6809Traits { { RW::Read, RW::Read, RW::Read, RW::Read, RW::NoData, RW::NoData, RW::NoData, RW::NoData, - RW::Read, RW::Read, RW::NoData, + RW::Read, RW::Read, RW::NoData, RW::NoData, } ); @@ -1235,7 +1236,7 @@ struct M6809Traits { { RW::Read, RW::Read, RW::Read, RW::Read, RW::NoData, - RW::Read, RW::Read, RW::NoData, + RW::Read, RW::Read, RW::NoData, RW::NoData, } ); } diff --git a/Processors/6809/6809.hpp b/Processors/6809/6809.hpp index ddf328ea2..ea1b7b674 100644 --- a/Processors/6809/6809.hpp +++ b/Processors/6809/6809.hpp @@ -666,7 +666,7 @@ struct Processor { ); address_.halves.high = registers_.reg(); - if(operation_.type == AccessType::LEA) { + if(operation_.operation == Operation::JMP) { goto internal_lic_break; } internal_cycle(LIC::Inactive); @@ -694,7 +694,7 @@ struct Processor { ++registers_.pc.full ); - if(operation_.type == AccessType::LEA) { + if(operation_.operation == Operation::JMP) { goto internal_lic_break; } internal_cycle(LIC::Inactive); @@ -766,7 +766,7 @@ struct Processor { read(BusState::Normal, LIC::Inactive, Literal(address_.full), operand_.halves.low, ++address_.full); address_ = operand_; - if(operation_.type == AccessType::LEA) { + if(operation_.operation == Operation::JMP) { goto internal_lic_break; } internal_cycle(LIC::Inactive); diff --git a/Processors/6809/Perform.hpp b/Processors/6809/Perform.hpp index 9da85153e..0310b106d 100644 --- a/Processors/6809/Perform.hpp +++ b/Processors/6809/Perform.hpp @@ -606,8 +606,7 @@ inline bool is_zero_costed(const InstructionSet::M6809::Operation operation) { case CLR: case LDA: case LDB: case STA: case STB: case LDD: case LDU: case LDX: case LDY: case LDS: case STD: case STU: case STX: case STY: case STS: - case LEAU: case LEAX: case LEAY: case LEAS: case SEX: - case TSTA: case TSTB: case JMP: + case SEX: case TSTA: case TSTB: case JMP: return true; } }