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Start promotion of ReturnType.
This commit is contained in:
Thomas Harte
parent
f96c33102a
commit
009915f4de
56
InstructionSets/x86/AccessType.hpp
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56
InstructionSets/x86/AccessType.hpp
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@ -0,0 +1,56 @@
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//
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// AccessType.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 05/11/2023.
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// Copyright © 2023 Thomas Harte. All rights reserved.
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//
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#ifndef AccessType_h
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#define AccessType_h
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namespace InstructionSet::x86 {
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/// Explains the type of access that `perform` intends to perform; is provided as a template parameter to whatever
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/// the caller supplies as `MemoryT` and `RegistersT` when obtaining a reference to whatever the processor
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/// intends to reference.
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///
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/// `perform` guarantees to validate all accesses before modifying any state, giving the caller opportunity to generate
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/// any exceptions that might be applicable.
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enum class AccessType {
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/// The requested value will be read from.
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Read,
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/// The requested value will be written to.
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Write,
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/// The requested value will be read from and then written to.
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ReadModifyWrite,
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/// The requested value has already been authorised for whatever form of access is now intended, so there's no
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/// need further to inspect. This is done e.g. by operations that will push multiple values to the stack to verify that
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/// all necessary stack space is available ahead of pushing anything, though each individual push will then result in
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/// a further `Preauthorised` access.
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PreauthorisedRead,
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};
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template <typename IntT, AccessType type> struct ReturnType;
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// Reads: return a value directly.
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template <typename IntT> struct ReturnType<IntT, AccessType::Read> { using type = IntT; };
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template <typename IntT> struct ReturnType<IntT, AccessType::PreauthorisedRead> { using type = IntT; };
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// Writes: return a custom type that can be written but not read.
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template <typename IntT>
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class Writeable {
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public:
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Writeable(IntT &target) : target_(target) {}
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void operator=(IntT value) { target_ = value; }
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private:
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IntT &target_;
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};
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template <typename IntT> struct ReturnType<IntT, AccessType::Write> { using type = Writeable<IntT>; };
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// Read-modify-writes: return a reference.
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template <typename IntT> struct ReturnType<IntT, AccessType::ReadModifyWrite> { using type = IntT &; };
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}
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#endif /* AccessType_h */
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@ -13,199 +13,13 @@
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#include "../../../Numeric/Carry.hpp"
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#include "../../../Numeric/RegisterSizes.hpp"
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#include "../Interrupts.hpp"
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#include "../AccessType.hpp"
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#include "Resolver.hpp"
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#include <utility>
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namespace InstructionSet::x86 {
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template <typename IntT, AccessType access, typename InstructionT, typename ContextT>
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IntT *resolve(
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InstructionT &instruction,
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Source source,
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DataPointer pointer,
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ContextT &context,
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IntT *none = nullptr,
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IntT *immediate = nullptr
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);
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/// Calculates the absolute address for @c pointer given the registers and memory provided in @c context and taking any
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/// referenced offset from @c instruction.
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template <Source source, typename IntT, AccessType access, typename InstructionT, typename ContextT>
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uint32_t address(
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InstructionT &instruction,
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DataPointer pointer,
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ContextT &context
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) {
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if constexpr (source == Source::DirectAddress) {
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return instruction.offset();
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}
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uint32_t address;
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uint16_t zero = 0;
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address = *resolve<uint16_t, access>(instruction, pointer.index(), pointer, context, &zero);
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if constexpr (is_32bit(ContextT::model)) {
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address <<= pointer.scale();
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}
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address += instruction.offset();
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if constexpr (source == Source::IndirectNoBase) {
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return address;
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}
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return address + *resolve<uint16_t, access>(instruction, pointer.base(), pointer, context);
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}
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/// @returns a pointer to the contents of the register identified by the combination of @c IntT and @c Source if any;
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/// @c nullptr otherwise. @c access is currently unused but is intended to provide the hook upon which updates to
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/// segment registers can be tracked for protected modes.
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template <typename IntT, AccessType access, Source source, typename ContextT>
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IntT *register_(ContextT &context) {
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static constexpr bool supports_dword = is_32bit(ContextT::model);
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switch(source) {
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case Source::eAX:
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// Slightly contorted if chain here and below:
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//
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// (i) does the `constexpr` version of a `switch`; and
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// (i) ensures .eax() etc aren't called on @c registers for 16-bit processors, so they need not implement 32-bit storage.
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.eax(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.ax(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.al(); }
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else { return nullptr; }
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case Source::eCX:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ecx(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.cx(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.cl(); }
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else { return nullptr; }
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case Source::eDX:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.edx(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.dx(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.dl(); }
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else if constexpr (std::is_same_v<IntT, uint32_t>) { return nullptr; }
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case Source::eBX:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ebx(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.bx(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.bl(); }
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else if constexpr (std::is_same_v<IntT, uint32_t>) { return nullptr; }
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case Source::eSPorAH:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.esp(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.sp(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.ah(); }
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else { return nullptr; }
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case Source::eBPorCH:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ebp(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.bp(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.ch(); }
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else { return nullptr; }
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case Source::eSIorDH:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.esi(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.si(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.dh(); }
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else { return nullptr; }
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case Source::eDIorBH:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.edi(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.di(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.bh(); }
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else { return nullptr; }
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// Segment registers are always 16-bit.
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case Source::ES: if constexpr (std::is_same_v<IntT, uint16_t>) return &context.registers.es(); else return nullptr;
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case Source::CS: if constexpr (std::is_same_v<IntT, uint16_t>) return &context.registers.cs(); else return nullptr;
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case Source::SS: if constexpr (std::is_same_v<IntT, uint16_t>) return &context.registers.ss(); else return nullptr;
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case Source::DS: if constexpr (std::is_same_v<IntT, uint16_t>) return &context.registers.ds(); else return nullptr;
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// 16-bit models don't have FS and GS.
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case Source::FS: if constexpr (is_32bit(ContextT::model) && std::is_same_v<IntT, uint16_t>) return &context.registers.fs(); else return nullptr;
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case Source::GS: if constexpr (is_32bit(ContextT::model) && std::is_same_v<IntT, uint16_t>) return &context.registers.gs(); else return nullptr;
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default: return nullptr;
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}
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}
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///Obtains the address described by @c pointer from @c instruction given the registers and memory as described by @c context.
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template <typename IntT, AccessType access, typename InstructionT, typename ContextT>
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uint32_t address(
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InstructionT &instruction,
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DataPointer pointer,
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ContextT &context
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) {
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// TODO: at least on the 8086 this isn't how register 'addresses' are resolved; instead whatever was the last computed address
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// remains in the address register and is returned. Find out what other x86s do and make a decision.
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switch(pointer.source()) {
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default: return 0;
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case Source::eAX: return *register_<IntT, access, Source::eAX>(context);
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case Source::eCX: return *register_<IntT, access, Source::eCX>(context);
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case Source::eDX: return *register_<IntT, access, Source::eDX>(context);
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case Source::eBX: return *register_<IntT, access, Source::eBX>(context);
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case Source::eSPorAH: return *register_<IntT, access, Source::eSPorAH>(context);
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case Source::eBPorCH: return *register_<IntT, access, Source::eBPorCH>(context);
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case Source::eSIorDH: return *register_<IntT, access, Source::eSIorDH>(context);
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case Source::eDIorBH: return *register_<IntT, access, Source::eDIorBH>(context);
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case Source::Indirect: return address<Source::Indirect, IntT, access>(instruction, pointer, context);
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case Source::IndirectNoBase: return address<Source::IndirectNoBase, IntT, access>(instruction, pointer, context);
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case Source::DirectAddress: return address<Source::DirectAddress, IntT, access>(instruction, pointer, context);
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}
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}
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/// Obtain a pointer to the value desribed by @c source, which is one of those named by @c pointer, using @c instruction and @c context
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/// for offsets, registers and memory contents.
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///
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/// If @c source is Source::None then @c none is returned.
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///
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/// If @c source is Source::Immediate then the appropriate portion of @c instrucion's operand
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/// is copied to @c *immediate and @c immediate is returned.
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template <typename IntT, AccessType access, typename InstructionT, typename ContextT>
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IntT *resolve(
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InstructionT &instruction,
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Source source,
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DataPointer pointer,
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ContextT &context,
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IntT *none,
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IntT *immediate
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) {
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// Rules:
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//
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// * if this is a memory access, set target_address and break;
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// * otherwise return the appropriate value.
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uint32_t target_address;
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switch(source) {
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// Defer all register accesses to the register-specific lookup.
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case Source::eAX: return register_<IntT, access, Source::eAX>(context);
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case Source::eCX: return register_<IntT, access, Source::eCX>(context);
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case Source::eDX: return register_<IntT, access, Source::eDX>(context);
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case Source::eBX: return register_<IntT, access, Source::eBX>(context);
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case Source::eSPorAH: return register_<IntT, access, Source::eSPorAH>(context);
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case Source::eBPorCH: return register_<IntT, access, Source::eBPorCH>(context);
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case Source::eSIorDH: return register_<IntT, access, Source::eSIorDH>(context);
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case Source::eDIorBH: return register_<IntT, access, Source::eDIorBH>(context);
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case Source::ES: return register_<IntT, access, Source::ES>(context);
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case Source::CS: return register_<IntT, access, Source::CS>(context);
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case Source::SS: return register_<IntT, access, Source::SS>(context);
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case Source::DS: return register_<IntT, access, Source::DS>(context);
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case Source::FS: return register_<IntT, access, Source::FS>(context);
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case Source::GS: return register_<IntT, access, Source::GS>(context);
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case Source::None: return none;
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case Source::Immediate:
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*immediate = instruction.operand();
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return immediate;
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case Source::Indirect:
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target_address = address<Source::Indirect, IntT, access>(instruction, pointer, context);
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break;
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case Source::IndirectNoBase:
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target_address = address<Source::IndirectNoBase, IntT, access>(instruction, pointer, context);
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break;
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case Source::DirectAddress:
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target_address = address<Source::DirectAddress, IntT, access>(instruction, pointer, context);
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break;
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}
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// If execution has reached here then a memory fetch is required.
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// Do it and exit.
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return &context.memory.template access<IntT, access>(instruction.data_segment(), target_address);
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};
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namespace Primitive {
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// The below takes a reference in order properly to handle PUSH SP,
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207
InstructionSets/x86/Implementation/Resolver.hpp
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207
InstructionSets/x86/Implementation/Resolver.hpp
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//
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// Resolver.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 05/11/2023.
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// Copyright © 2023 Thomas Harte. All rights reserved.
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//
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#ifndef Resolver_h
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#define Resolver_h
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#include "../AccessType.hpp"
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namespace InstructionSet::x86 {
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/// Obtain a pointer to the value desribed by @c source, which is one of those named by @c pointer, using @c instruction and @c context
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/// for offsets, registers and memory contents.
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///
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/// If @c source is Source::None then @c none is returned.
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///
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/// If @c source is Source::Immediate then the appropriate portion of @c instrucion's operand
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/// is copied to @c *immediate and @c immediate is returned.
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template <typename IntT, AccessType access, typename InstructionT, typename ContextT>
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IntT *resolve(
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InstructionT &instruction,
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Source source,
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DataPointer pointer,
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ContextT &context,
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IntT *none = nullptr,
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IntT *immediate = nullptr
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);
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/// Calculates the absolute address for @c pointer given the registers and memory provided in @c context and taking any
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/// referenced offset from @c instruction.
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template <Source source, typename IntT, AccessType access, typename InstructionT, typename ContextT>
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uint32_t address(
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InstructionT &instruction,
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DataPointer pointer,
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ContextT &context
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) {
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if constexpr (source == Source::DirectAddress) {
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return instruction.offset();
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}
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uint32_t address;
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uint16_t zero = 0;
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address = *resolve<uint16_t, access>(instruction, pointer.index(), pointer, context, &zero);
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if constexpr (is_32bit(ContextT::model)) {
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address <<= pointer.scale();
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}
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address += instruction.offset();
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if constexpr (source == Source::IndirectNoBase) {
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return address;
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}
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return address + *resolve<uint16_t, access>(instruction, pointer.base(), pointer, context);
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}
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/// @returns a pointer to the contents of the register identified by the combination of @c IntT and @c Source if any;
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/// @c nullptr otherwise. @c access is currently unused but is intended to provide the hook upon which updates to
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/// segment registers can be tracked for protected modes.
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template <typename IntT, AccessType access, Source source, typename ContextT>
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IntT *register_(ContextT &context) {
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static constexpr bool supports_dword = is_32bit(ContextT::model);
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switch(source) {
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case Source::eAX:
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// Slightly contorted if chain here and below:
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//
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// (i) does the `constexpr` version of a `switch`; and
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// (i) ensures .eax() etc aren't called on @c registers for 16-bit processors, so they need not implement 32-bit storage.
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.eax(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.ax(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.al(); }
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else { return nullptr; }
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case Source::eCX:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ecx(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.cx(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.cl(); }
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else { return nullptr; }
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case Source::eDX:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.edx(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.dx(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.dl(); }
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else if constexpr (std::is_same_v<IntT, uint32_t>) { return nullptr; }
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case Source::eBX:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ebx(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.bx(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.bl(); }
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else if constexpr (std::is_same_v<IntT, uint32_t>) { return nullptr; }
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case Source::eSPorAH:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.esp(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.sp(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.ah(); }
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else { return nullptr; }
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case Source::eBPorCH:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ebp(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.bp(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.ch(); }
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else { return nullptr; }
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case Source::eSIorDH:
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if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.esi(); }
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else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.si(); }
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else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.dh(); }
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else { return nullptr; }
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case Source::eDIorBH:
|
||||
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.edi(); }
|
||||
else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.di(); }
|
||||
else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.bh(); }
|
||||
else { return nullptr; }
|
||||
|
||||
// Segment registers are always 16-bit.
|
||||
case Source::ES: if constexpr (std::is_same_v<IntT, uint16_t>) return &context.registers.es(); else return nullptr;
|
||||
case Source::CS: if constexpr (std::is_same_v<IntT, uint16_t>) return &context.registers.cs(); else return nullptr;
|
||||
case Source::SS: if constexpr (std::is_same_v<IntT, uint16_t>) return &context.registers.ss(); else return nullptr;
|
||||
case Source::DS: if constexpr (std::is_same_v<IntT, uint16_t>) return &context.registers.ds(); else return nullptr;
|
||||
|
||||
// 16-bit models don't have FS and GS.
|
||||
case Source::FS: if constexpr (is_32bit(ContextT::model) && std::is_same_v<IntT, uint16_t>) return &context.registers.fs(); else return nullptr;
|
||||
case Source::GS: if constexpr (is_32bit(ContextT::model) && std::is_same_v<IntT, uint16_t>) return &context.registers.gs(); else return nullptr;
|
||||
|
||||
default: return nullptr;
|
||||
}
|
||||
}
|
||||
|
||||
///Obtains the address described by @c pointer from @c instruction given the registers and memory as described by @c context.
|
||||
template <typename IntT, AccessType access, typename InstructionT, typename ContextT>
|
||||
uint32_t address(
|
||||
InstructionT &instruction,
|
||||
DataPointer pointer,
|
||||
ContextT &context
|
||||
) {
|
||||
// TODO: at least on the 8086 this isn't how register 'addresses' are resolved; instead whatever was the last computed address
|
||||
// remains in the address register and is returned. Find out what other x86s do and make a decision.
|
||||
switch(pointer.source()) {
|
||||
default: return 0;
|
||||
case Source::eAX: return *register_<IntT, access, Source::eAX>(context);
|
||||
case Source::eCX: return *register_<IntT, access, Source::eCX>(context);
|
||||
case Source::eDX: return *register_<IntT, access, Source::eDX>(context);
|
||||
case Source::eBX: return *register_<IntT, access, Source::eBX>(context);
|
||||
case Source::eSPorAH: return *register_<IntT, access, Source::eSPorAH>(context);
|
||||
case Source::eBPorCH: return *register_<IntT, access, Source::eBPorCH>(context);
|
||||
case Source::eSIorDH: return *register_<IntT, access, Source::eSIorDH>(context);
|
||||
case Source::eDIorBH: return *register_<IntT, access, Source::eDIorBH>(context);
|
||||
case Source::Indirect: return address<Source::Indirect, IntT, access>(instruction, pointer, context);
|
||||
case Source::IndirectNoBase: return address<Source::IndirectNoBase, IntT, access>(instruction, pointer, context);
|
||||
case Source::DirectAddress: return address<Source::DirectAddress, IntT, access>(instruction, pointer, context);
|
||||
}
|
||||
}
|
||||
|
||||
// See forward declaration, above, for details.
|
||||
template <typename IntT, AccessType access, typename InstructionT, typename ContextT>
|
||||
IntT *resolve(
|
||||
InstructionT &instruction,
|
||||
Source source,
|
||||
DataPointer pointer,
|
||||
ContextT &context,
|
||||
IntT *none,
|
||||
IntT *immediate
|
||||
) {
|
||||
// Rules:
|
||||
//
|
||||
// * if this is a memory access, set target_address and break;
|
||||
// * otherwise return the appropriate value.
|
||||
uint32_t target_address;
|
||||
switch(source) {
|
||||
// Defer all register accesses to the register-specific lookup.
|
||||
case Source::eAX: return register_<IntT, access, Source::eAX>(context);
|
||||
case Source::eCX: return register_<IntT, access, Source::eCX>(context);
|
||||
case Source::eDX: return register_<IntT, access, Source::eDX>(context);
|
||||
case Source::eBX: return register_<IntT, access, Source::eBX>(context);
|
||||
case Source::eSPorAH: return register_<IntT, access, Source::eSPorAH>(context);
|
||||
case Source::eBPorCH: return register_<IntT, access, Source::eBPorCH>(context);
|
||||
case Source::eSIorDH: return register_<IntT, access, Source::eSIorDH>(context);
|
||||
case Source::eDIorBH: return register_<IntT, access, Source::eDIorBH>(context);
|
||||
case Source::ES: return register_<IntT, access, Source::ES>(context);
|
||||
case Source::CS: return register_<IntT, access, Source::CS>(context);
|
||||
case Source::SS: return register_<IntT, access, Source::SS>(context);
|
||||
case Source::DS: return register_<IntT, access, Source::DS>(context);
|
||||
case Source::FS: return register_<IntT, access, Source::FS>(context);
|
||||
case Source::GS: return register_<IntT, access, Source::GS>(context);
|
||||
|
||||
case Source::None: return none;
|
||||
|
||||
case Source::Immediate:
|
||||
*immediate = instruction.operand();
|
||||
return immediate;
|
||||
|
||||
case Source::Indirect:
|
||||
target_address = address<Source::Indirect, IntT, access>(instruction, pointer, context);
|
||||
break;
|
||||
case Source::IndirectNoBase:
|
||||
target_address = address<Source::IndirectNoBase, IntT, access>(instruction, pointer, context);
|
||||
break;
|
||||
case Source::DirectAddress:
|
||||
target_address = address<Source::DirectAddress, IntT, access>(instruction, pointer, context);
|
||||
break;
|
||||
}
|
||||
|
||||
// If execution has reached here then a memory fetch is required.
|
||||
// Do it and exit.
|
||||
return &context.memory.template access<IntT, access>(instruction.data_segment(), target_address);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif /* Resolver_h */
|
||||
|
|
@ -15,26 +15,6 @@
|
|||
|
||||
namespace InstructionSet::x86 {
|
||||
|
||||
/// Explains the type of access that `perform` intends to perform; is provided as a template parameter to whatever
|
||||
/// the caller supplies as `MemoryT` and `RegistersT` when obtaining a reference to whatever the processor
|
||||
/// intends to reference.
|
||||
///
|
||||
/// `perform` guarantees to validate all accesses before modifying any state, giving the caller opportunity to generate
|
||||
/// any exceptions that might be applicable.
|
||||
enum class AccessType {
|
||||
/// The requested value will be read from.
|
||||
Read,
|
||||
/// The requested value will be written to.
|
||||
Write,
|
||||
/// The requested value will be read from and then written to.
|
||||
ReadModifyWrite,
|
||||
/// The requested value has already been authorised for whatever form of access is now intended, so there's no
|
||||
/// need further to inspect. This is done e.g. by operations that will push multiple values to the stack to verify that
|
||||
/// all necessary stack space is available ahead of pushing anything, though each individual push will then result in
|
||||
/// a further `Preauthorised` access.
|
||||
PreauthorisedRead,
|
||||
};
|
||||
|
||||
template <
|
||||
Model model_,
|
||||
typename FlowControllerT,
|
||||
|
|
|
|||
|
|
@ -1150,6 +1150,8 @@
|
|||
42A5E8412ABBE16F00A0DD5D /* nop_test.bin */ = {isa = PBXFileReference; lastKnownFileType = archive.macbinary; path = nop_test.bin; sourceTree = "<group>"; };
|
||||
42A5E8422ABBE16F00A0DD5D /* lax_test.bin */ = {isa = PBXFileReference; lastKnownFileType = archive.macbinary; path = lax_test.bin; sourceTree = "<group>"; };
|
||||
42A5E8432ABBE16F00A0DD5D /* branch_backwards_test.bin */ = {isa = PBXFileReference; lastKnownFileType = archive.macbinary; path = branch_backwards_test.bin; sourceTree = "<group>"; };
|
||||
42AA41232AF888370016751C /* AccessType.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = AccessType.hpp; sourceTree = "<group>"; };
|
||||
42AA41242AF8893F0016751C /* Resolver.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Resolver.hpp; sourceTree = "<group>"; };
|
||||
42AD552E2A0C4D5000ACE410 /* 68000.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = 68000.hpp; sourceTree = "<group>"; };
|
||||
42AD55302A0C4D5000ACE410 /* 68000Storage.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = 68000Storage.hpp; sourceTree = "<group>"; };
|
||||
42AD55312A0C4D5000ACE410 /* 68000Implementation.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = 68000Implementation.hpp; sourceTree = "<group>"; };
|
||||
|
|
@ -2328,6 +2330,7 @@
|
|||
isa = PBXGroup;
|
||||
children = (
|
||||
42437B382ACF2798006DFED1 /* PerformImplementation.hpp */,
|
||||
42AA41242AF8893F0016751C /* Resolver.hpp */,
|
||||
);
|
||||
path = Implementation;
|
||||
sourceTree = "<group>";
|
||||
|
|
@ -4997,12 +5000,13 @@
|
|||
children = (
|
||||
4BEDA3B925B25563000C2DBD /* Decoder.cpp */,
|
||||
4B69DEB52AB79E4F0055B217 /* Instruction.cpp */,
|
||||
42AA41232AF888370016751C /* AccessType.hpp */,
|
||||
4BEDA3B825B25563000C2DBD /* Decoder.hpp */,
|
||||
42437B342ACF02A9006DFED1 /* Flags.hpp */,
|
||||
4BEDA3DB25B2588F000C2DBD /* Instruction.hpp */,
|
||||
42437B392AD07465006DFED1 /* Interrupts.hpp */,
|
||||
4BE3C69527CBC540000EAD28 /* Model.hpp */,
|
||||
42437B352ACF0AA2006DFED1 /* Perform.hpp */,
|
||||
42437B342ACF02A9006DFED1 /* Flags.hpp */,
|
||||
42437B372ACF2798006DFED1 /* Implementation */,
|
||||
);
|
||||
path = x86;
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include "NSData+dataWithContentsOfGZippedFile.h"
|
||||
|
||||
#include "../../../InstructionSets/x86/AccessType.hpp"
|
||||
#include "../../../InstructionSets/x86/Decoder.hpp"
|
||||
#include "../../../InstructionSets/x86/Perform.hpp"
|
||||
#include "../../../InstructionSets/x86/Flags.hpp"
|
||||
|
|
@ -97,16 +98,6 @@ struct Memory {
|
|||
public:
|
||||
using AccessType = InstructionSet::x86::AccessType;
|
||||
|
||||
template <typename IntT, AccessType type> struct ReturnType;
|
||||
|
||||
// Reads: return a value directly.
|
||||
template <typename IntT> struct ReturnType<IntT, AccessType::Read> { using type = IntT; };
|
||||
template <typename IntT> struct ReturnType<IntT, AccessType::PreauthorisedRead> { using type = IntT; };
|
||||
|
||||
// Writes: return a reference.
|
||||
template <typename IntT> struct ReturnType<IntT, AccessType::Write> { using type = IntT &; };
|
||||
template <typename IntT> struct ReturnType<IntT, AccessType::ReadModifyWrite> { using type = IntT &; };
|
||||
|
||||
// Constructor.
|
||||
Memory(Registers ®isters) : registers_(registers) {
|
||||
memory.resize(1024*1024);
|
||||
|
|
@ -162,7 +153,7 @@ struct Memory {
|
|||
|
||||
// Accesses an address based on segment:offset.
|
||||
template <typename IntT, AccessType type>
|
||||
typename ReturnType<IntT, type>::type &access(InstructionSet::x86::Source segment, uint16_t offset) {
|
||||
typename InstructionSet::x86::ReturnType<IntT, type>::type &access(InstructionSet::x86::Source segment, uint16_t offset) {
|
||||
if constexpr (std::is_same_v<IntT, uint16_t>) {
|
||||
// If this is a 16-bit access that runs past the end of the segment, it'll wrap back
|
||||
// to the start. So the 16-bit value will need to be a local cache.
|
||||
|
|
@ -185,7 +176,7 @@ struct Memory {
|
|||
|
||||
// Accesses an address based on physical location.
|
||||
template <typename IntT, AccessType type>
|
||||
typename ReturnType<IntT, type>::type &access(uint32_t address) {
|
||||
typename InstructionSet::x86::ReturnType<IntT, type>::type &access(uint32_t address) {
|
||||
return access<IntT, type>(address, Tag::Accessed);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user