From c0eb401d04d695f8a6bb4c15608b677efd06bd25 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sat, 5 Aug 2023 14:57:43 -0400
Subject: [PATCH] Add a between-instructions enforcement of SH = 1.

---
 Processors/65816/Implementation/65816Implementation.hpp | 3 +++
 Processors/65816/Implementation/65816Storage.cpp        | 3 +--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp
index 9bd0b8902..b980bbe73 100644
--- a/Processors/65816/Implementation/65816Implementation.hpp
+++ b/Processors/65816/Implementation/65816Implementation.hpp
@@ -67,6 +67,9 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
 					last_operation_pc_ = registers_.pc;
 					last_operation_program_bank_ = uint8_t(registers_.program_bank >> 16);
 					memory_lock_ = false;
+
+					// Reenforce the top byte of S if applicable.
+					registers_.s.halves.high = stack_address();
 				} continue;
 
 				case OperationDecode: {
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index 99be184ed..a53468ee3 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -1131,11 +1131,10 @@ void ProcessorStorage::set_emulation_mode(bool enabled) {
 		set_m_x_flags(true, true);
 		registers_.e_masks[0] = 0xff00;
 		registers_.e_masks[1] = 0x00ff;
+		registers_.s.halves.high = 1;
 	} else {
 		registers_.e_masks[0] = 0x0000;
 		registers_.e_masks[1] = 0xffff;
-		registers_.s.halves.high = 1;	// To pretend it was 1 all along; this implementation actually ignores
-										// the top byte while in emulation mode.
 	}
 }