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https://github.com/TomHarte/CLK.git
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Added the ability to set a port input, and relaxed bus state testing. I think my on-demand bus reactions here are inappropriate, so more work to do here probably.
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@ -231,6 +231,10 @@ uint8_t AY38910::get_port_output(bool port_b) {
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return registers_[port_b ? 15 : 14];
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return registers_[port_b ? 15 : 14];
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}
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}
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void AY38910::set_port_input(bool port_b, uint8_t value) {
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registers_[port_b ? 15 : 14] = value;
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}
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void AY38910::set_data_input(uint8_t r) {
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void AY38910::set_data_input(uint8_t r) {
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data_input_ = r;
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data_input_ = r;
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}
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}
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@ -252,7 +256,7 @@ void AY38910::set_control_lines(ControlLines control_lines) {
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case (int)(BDIR | BC2): new_state = Write; break;
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case (int)(BDIR | BC2): new_state = Write; break;
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}
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}
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if(new_state != control_state_) {
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// if(new_state != control_state_) {
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control_state_ = new_state;
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control_state_ = new_state;
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switch(new_state) {
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switch(new_state) {
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default: break;
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default: break;
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@ -260,5 +264,5 @@ void AY38910::set_control_lines(ControlLines control_lines) {
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case Write: set_register_value(data_input_); break;
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case Write: set_register_value(data_input_); break;
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case Read: data_output_ = get_register_value(); break;
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case Read: data_output_ = get_register_value(); break;
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}
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}
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}
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// }
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}
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}
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@ -47,6 +47,12 @@ class AY38910: public ::Outputs::Filter<AY38910> {
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*/
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*/
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uint8_t get_port_output(bool port_b);
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uint8_t get_port_output(bool port_b);
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/*!
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Sets the value that would appear on the requested interface port if it were in output mode.
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@parameter port_b @c true to get the value for Port B, @c false to get the value for Port A.
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*/
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void set_port_input(bool port_b, uint8_t value);
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// to satisfy ::Outputs::Speaker (included via ::Outputs::Filter; not for public consumption
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// to satisfy ::Outputs::Speaker (included via ::Outputs::Filter; not for public consumption
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void get_samples(unsigned int number_of_samples, int16_t *target);
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void get_samples(unsigned int number_of_samples, int16_t *target);
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