ADD/SUBQ #, An shouldn't set flags.

Also, temporarily at least, adds a new means for observing CPU behaviour.

Processors/68000/68000.hpp

@@ -186,6 +186,11 @@ class BusHandler {
 		}
 
 		void flush() {}
+
+		/*!
+			Provides information about the path of execution if enabled via the template.
+		*/
+		void will_perform(uint32_t address, uint16_t opcode) {}
 };
 
 #include "Implementation/68000Storage.hpp"
@@ -205,7 +210,7 @@ struct ProcessorState {
 //			uint16_t current_instruction;
 };
 
-template <class T, bool dtack_is_implicit> class Processor: public ProcessorBase {
+template <class T, bool dtack_is_implicit, bool signal_will_perform = false> class Processor: public ProcessorBase {
 	public:
 		Processor(T &bus_handler) : ProcessorBase(), bus_handler_(bus_handler) {}
 

Processors/68000/Implementation/68000Implementation.hpp

@@ -36,7 +36,7 @@
 	trace_flag_			= (x) & 0x8000;	\
 	set_is_supervisor(!!(((x) >> 13) & 1));
 
-template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>::run_for(HalfCycles duration) {
+template <class T, bool dtack_is_implicit, bool signal_will_perform> void Processor<T, dtack_is_implicit, signal_will_perform>::run_for(HalfCycles duration) {
 	HalfCycles remaining_duration = duration + half_cycles_left_to_run_;
 	while(remaining_duration > HalfCycles(0)) {
 		/*
@@ -52,22 +52,19 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
 						// no instruction was ongoing. Either way, do a standard instruction operation.
 
 						// TODO: unless an interrupt is pending, or the trap flag is set.
-//						static bool should_log = false;
+#ifdef LOG_TRACE
-
+						std::cout << std::setfill('0');
-//						should_log |= program_counter_.full >= 0x4F54 && program_counter_.full <= 0x4F84;
+						std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
-//						if(should_log) {
+						std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
-							std::cout << std::setfill('0');
+						for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
-							std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
+						for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
-							std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
+						if(is_supervisor_) {
-							for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
+							std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " ";
-							for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
+						} else {
-							if(is_supervisor_) {
+							std::cout << "ssp:" << std::setw(8) << std::setfill('0') << stack_pointers_[1].full << " ";
-								std::cout << "usp:" << std::setw(8) << std::setfill('0') << stack_pointers_[0].full << " ";
+						}
-							} else {
+						std::cout << '\n';
-								std::cout << "ssp:" << std::setw(8) << std::setfill('0') << stack_pointers_[1].full << " ";
+#endif
-							}
-							std::cout << '\n';
-//						}
 
 						decoded_instruction_ = prefetch_queue_.halves.high.full;
 						if(!instructions[decoded_instruction_].micro_operations) {
@@ -75,13 +72,17 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
 							std::cerr << "68000 Abilities exhausted; can't manage instruction " << std::hex << decoded_instruction_ << " from " << (program_counter_.full - 4) << std::endl;
 							return;
 						} else {
-//							if(0x4f7a == program_counter_.full - 4) return;
+#ifdef LOG_TRACE
 							std::cout << std::hex << (program_counter_.full - 4) << ": " << std::setw(4) << decoded_instruction_ << '\t';
+#endif
+						}
+
+						if(signal_will_perform) {
+							bus_handler_.will_perform(program_counter_.full - 4, decoded_instruction_);
 						}
 
 						active_program_ = &instructions[decoded_instruction_];
 						active_micro_op_ = active_program_->micro_operations;
-
 					}
 
 					auto bus_program = active_micro_op_->bus_program;
@@ -237,6 +238,14 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
 											active_program_->destination->full);
 								} break;
 
+								case Operation::ADDQAl:
+									active_program_->destination->full += q();
+								break;
+
+								case Operation::SUBQAl:
+									active_program_->destination->full -= q();
+								break;
+
 #undef addl
 #undef addw
 #undef addb
@@ -264,6 +273,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
 									active_program_->destination->full -= active_program_->source->full;
 								break;
 
+
 								// BRA: alters the program counter, exclusively via the prefetch queue.
 								case Operation::BRA: {
 									const int8_t byte_offset = int8_t(prefetch_queue_.halves.high.halves.low);
@@ -1377,6 +1387,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
 				active_step_->microcycle.length +
 				bus_handler_.perform_bus_operation(active_step_->microcycle, is_supervisor_);
 
+#ifdef LOG_TRACE
 			if(!(active_step_->microcycle.operation & Microcycle::IsProgram)) {
 				switch(active_step_->microcycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
 					default: break;
@@ -1395,7 +1406,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
 					break;
 				}
 			}
-
+#endif
 
 		/*
 			PERFORM THE BUS STEP'S ACTION.
@@ -1426,7 +1437,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
 	half_cycles_left_to_run_ = remaining_duration;
 }
 
-template <class T, bool dtack_is_implicit> ProcessorState Processor<T, dtack_is_implicit>::get_state() {
+template <class T, bool dtack_is_implicit, bool signal_will_perform> ProcessorState Processor<T, dtack_is_implicit, signal_will_perform>::get_state() {
 	write_back_stack_pointer();
 
 	State state;
@@ -1440,7 +1451,7 @@ template <class T, bool dtack_is_implicit> ProcessorState Processor<T, dtack_is_
 	return state;
 }
 
-template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>::set_state(const ProcessorState &state) {
+template <class T, bool dtack_is_implicit, bool signal_will_perform> void Processor<T, dtack_is_implicit, signal_will_perform>::set_state(const ProcessorState &state) {
 	memcpy(data_, state.data, sizeof(state.data));
 	memcpy(address_, state.address, sizeof(state.address));
 	stack_pointers_[0].full = state.user_stack_pointer;

Processors/68000/Implementation/68000Storage.cpp

@@ -1314,6 +1314,20 @@ struct ProcessorStorageConstructor {
 							storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
 
 							const int mode = combined_mode(ea_mode, ea_register);
+
+							// If the destination is an address register then byte mode isn't allowed, and
+							// flags shouldn't be affected (so, a different operation is used).
+							if(mode == An) {
+								if(is_byte_access) continue;
+								switch(operation) {
+									default: break;
+									case Operation::ADDQl:	// TODO: should the adds be distinguished? If so, how?
+									case Operation::ADDQw:	operation = Operation::ADDQAl;	break;
+									case Operation::SUBQl:
+									case Operation::SUBQw:	operation = Operation::SUBQAl;	break;
+								}
+							}
+
 							switch(is_long_word_access ? l(mode) : bw(mode)) {
 								default: continue;
 
@@ -3061,6 +3075,8 @@ CPU::MC68000::ProcessorStorage::ProcessorStorage() {
 	active_step_ = reset_bus_steps_;
 	effective_address_[0] = 0;
 	is_supervisor_ = 1;
+	interrupt_level_ = 7;
+	address_[7] = 0x00030000;
 }
 
 void CPU::MC68000::ProcessorStorage::write_back_stack_pointer() {

Processors/68000/Implementation/68000Storage.hpp

@@ -49,10 +49,12 @@ class ProcessorStorage {
 			ADDb,	ADDw,	ADDl,
 			ADDQb,	ADDQw,	ADDQl,
 			ADDAw,	ADDAl,
+			ADDQAw,	ADDQAl,
 
 			SUBb,	SUBw,	SUBl,
 			SUBQb,	SUBQw,	SUBQl,
 			SUBAw,	SUBAl,
+			SUBQAw,	SUBQAl,
 
 			MOVEb,	MOVEw,	MOVEl,	MOVEq,
 			MOVEAw,	MOVEAl,