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Ensures the Mac uses auto vectored interrupts.
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3bb8d6717f
commit
0848fc7e03
@ -176,10 +176,19 @@ class ConcreteMachine:
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if(!(operation & Microcycle::Read) || word_address >= 0x300000) operation = 0;
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if(!(operation & Microcycle::Read) || word_address >= 0x300000) operation = 0;
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}
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}
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switch(operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
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const auto masked_operation = operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge);
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switch(masked_operation) {
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default:
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default:
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break;
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break;
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// Catches the deliberation set of operation to 0 above.
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case 0: break;
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case Microcycle::InterruptAcknowledge | Microcycle::SelectByte:
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// The Macintosh uses autovectored interrupts.
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mc68000_.set_is_peripheral_address(true);
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break;
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case Microcycle::SelectWord | Microcycle::Read:
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = memory_base[word_address];
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cycle.value->full = memory_base[word_address];
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break;
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break;
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@ -272,7 +272,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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}
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}
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#ifdef LOG_TRACE
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#ifdef LOG_TRACE
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// should_log |= ((program_counter_.full - 4) == 0x4058d8);
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should_log |= ((program_counter_.full - 4) == 0x4058d8);
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#endif
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#endif
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if(instructions[decoded_instruction_.full].micro_operations) {
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if(instructions[decoded_instruction_.full].micro_operations) {
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@ -1859,6 +1859,9 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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break;
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break;
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case int(MicroOp::Action::PrepareINTVector):
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case int(MicroOp::Action::PrepareINTVector):
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// Let bus error go back to causing exceptions.
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is_starting_interrupt_ = false;
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// Bus error => spurious interrupt.
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// Bus error => spurious interrupt.
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if(bus_error_) {
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if(bus_error_) {
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effective_address_[0].full = 24 << 2;
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effective_address_[0].full = 24 << 2;
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@ -1873,9 +1876,6 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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// Otherwise, the vector is whatever we were just told it is.
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// Otherwise, the vector is whatever we were just told it is.
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effective_address_[0].full = source_bus_data_[0].halves.low.halves.low << 2;
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effective_address_[0].full = source_bus_data_[0].halves.low.halves.low << 2;
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// Let bus error go back to causing exceptions.
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is_starting_interrupt_ = false;
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break;
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break;
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case int(MicroOp::Action::CopyNextWord):
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case int(MicroOp::Action::CopyNextWord):
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