From 0af8660181533f6f18c139d58efc85688ee5fcba Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 9 May 2022 16:19:25 -0400 Subject: [PATCH] Remove `add_pc` and `decline_branch` in favour of operation-specific signals. --- InstructionSets/M68k/Executor.hpp | 4 +- .../Implementation/ExecutorImplementation.hpp | 14 ++++- .../Implementation/PerformImplementation.hpp | 63 ++++++++----------- .../68000ComparativeTests.mm | 2 +- .../Implementation/68000Implementation.hpp | 4 +- 5 files changed, 42 insertions(+), 45 deletions(-) diff --git a/InstructionSets/M68k/Executor.hpp b/InstructionSets/M68k/Executor.hpp index 1256a5cce..29a40cc8a 100644 --- a/InstructionSets/M68k/Executor.hpp +++ b/InstructionSets/M68k/Executor.hpp @@ -49,12 +49,12 @@ template class Executor { // Flow control. void consume_cycles(int) {} void set_pc(uint32_t); - void add_pc(uint32_t); - void decline_branch() {} void raise_exception(int, bool use_current_instruction_pc = true); void did_update_status(); + template void complete_bcc(bool matched_condition, IntT offset); + void complete_dbcc(bool matched_condition, bool overflowed, int16_t offset); void stop(); void bsr(uint32_t offset); void jsr(uint32_t offset); diff --git a/InstructionSets/M68k/Implementation/ExecutorImplementation.hpp b/InstructionSets/M68k/Implementation/ExecutorImplementation.hpp index c1f3dc08a..096b3b8c2 100644 --- a/InstructionSets/M68k/Implementation/ExecutorImplementation.hpp +++ b/InstructionSets/M68k/Implementation/ExecutorImplementation.hpp @@ -330,7 +330,6 @@ void Executor::set_state(const Registers &state) { } // MARK: - Flow Control. -// TODO: flow control, all below here. template void Executor::raise_exception(int index, bool use_current_instruction_pc) { @@ -367,8 +366,17 @@ void Executor::set_pc(uint32_t address) { } template -void Executor::add_pc(uint32_t offset) { - program_counter_.l = instruction_address_ + offset; +template void Executor::complete_bcc(bool branch, IntT offset) { + if(branch) { + program_counter_.l = instruction_address_ + offset + 2; + } +} + +template +void Executor::complete_dbcc(bool matched_condition, bool overflowed, int16_t offset) { + if(!matched_condition && !overflowed) { + program_counter_.l = instruction_address_ + offset + 2; + } } template diff --git a/InstructionSets/M68k/Implementation/PerformImplementation.hpp b/InstructionSets/M68k/Implementation/PerformImplementation.hpp index 2c4e5463f..2fa913521 100644 --- a/InstructionSets/M68k/Implementation/PerformImplementation.hpp +++ b/InstructionSets/M68k/Implementation/PerformImplementation.hpp @@ -254,27 +254,21 @@ template < // Special case: the condition code is 1, which is ordinarily false. In that case this // is the trailing step of a BSR. case Operation::Bccb: - if(status.evaluate_condition(instruction.condition())) { - flow_controller.add_pc(int8_t(src.b) + 2); - } else { - flow_controller.decline_branch(); - } + flow_controller.template complete_bcc( + status.evaluate_condition(instruction.condition()), + src.b); break; case Operation::Bccw: - if(status.evaluate_condition(instruction.condition())) { - flow_controller.add_pc(int16_t(src.w) + 2); - } else { - flow_controller.decline_branch(); - } + flow_controller.template complete_bcc( + status.evaluate_condition(instruction.condition()), + src.w); break; case Operation::Bccl: - if(status.evaluate_condition(instruction.condition())) { - flow_controller.add_pc(src.l + 2); - } else { - flow_controller.decline_branch(); - } + flow_controller.template complete_bcc( + status.evaluate_condition(instruction.condition()), + src.l); break; case Operation::BSRb: @@ -287,23 +281,22 @@ template < flow_controller.bsr(src.l + 2); break; - case Operation::DBcc: - // Decide what sort of DBcc this is. - if(!status.evaluate_condition(instruction.condition())) { - -- src.w; + case Operation::DBcc: { + const bool matched_condition = status.evaluate_condition(instruction.condition()); + bool overflowed = false; - if(src.w == 0xffff) { - // This DBcc will be ignored as the counter has underflowed. - flow_controller.decline_branch(); - } else { - // Take the branch. - flow_controller.add_pc(int16_t(dest.l) + 2); - } - } else { - // This DBcc will be ignored as the condition is true. - flow_controller.decline_branch(); + // Classify the dbcc. + if(!matched_condition) { + -- src.w; + overflowed = src.w == 0xffff; } - break; + + // Take the branch. + flow_controller.complete_dbcc( + matched_condition, + overflowed, + int16_t(dest.w)); + } break; case Operation::Scc: src.b = status.evaluate_condition(instruction.condition()) ? 0xff : 0x00; @@ -427,9 +420,9 @@ template < dest.l = src.l; break; -// case Operation::PEA: -// destination_bus_data_ = effective_address_[0]; -// break; + case Operation::PEA: + flow_controller.pea(src.l); + break; /* Status word moves and manipulations. @@ -1205,10 +1198,6 @@ template < flow_controller.template movem_toM(instruction, src.l, dest.l); break; - case Operation::PEA: - flow_controller.pea(src.l); - break; - /* RTE and RTR share an implementation. */ diff --git a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm index fa707dde5..c5c6792ef 100644 --- a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm +++ b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm @@ -30,7 +30,7 @@ - (void)setUp { // To limit tests run to a subset of files and/or of tests, uncomment and fill in below. -// _fileSet = [NSSet setWithArray:@[@"chk.json"]]; + _fileSet = [NSSet setWithArray:@[@"dbcc.json"]]; // _testSet = [NSSet setWithArray:@[@"CHK 4190"]]; // _fileSet = [NSSet setWithArray:@[@"jmp_jsr.json"]]; // _testSet = [NSSet setWithArray:@[@"CHK 41a8"]]; diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp index 2469a6ef8..812d2a0ab 100644 --- a/Processors/68000/Implementation/68000Implementation.hpp +++ b/Processors/68000/Implementation/68000Implementation.hpp @@ -1766,7 +1766,7 @@ template void Proces } break; case Operation::ROLb: rol(destination()->halves.low.halves.low, 8); break; case Operation::ROLw: rol(destination()->halves.low.full, 16); break; - case Operation::ROLl: rol(destination()->full, 32); break; + case Operation::ROLl: rol(destination()->full, 32); break; #define ror(destination, size) { \ @@ -1795,7 +1795,7 @@ template void Proces } break; case Operation::RORb: ror(destination()->halves.low.halves.low, 8); break; case Operation::RORw: ror(destination()->halves.low.full, 16); break; - case Operation::RORl: ror(destination()->full, 32); break; + case Operation::RORl: ror(destination()->full, 32); break; #define roxl(destination, size) { \ decode_shift_count(); \