6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-01-11 08:30:55 +00:00
Code Issues Projects Releases Wiki Activity

Add details on gaps in coverage.

Browse Source
This commit is contained in:
Thomas Harte 2022-05-25 15:36:27 -04:00
parent 5eb19da91f
commit 0bedf608c0
1 changed files with 20 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
OSBindings/Mac/Clock SignalTests/68000 Comparative Tests/readme.md
View File

@ -40,6 +40,25 @@ All initial register contents are random except that the lowest bit is never set
So the output is very scattergun approach, with a lot of redundancy.
## Known Issues
Errors in generation mean that:
1. MOVE is mostly untested; MOVEq is well-tested and other MOVEs appear within the test set as per the approximate generation algorithm above but due to an error in the generation of move.json, all of its opcodes are $2000 less than they should be, causing them to hit various instructions other than MOVE;
2. there is sparse coverage of the rotates and shifts: LS[L/R], AS[L/R], RO[L/R] and ROX[L/R]; and
3. there are similarly few tests of MULU.
Issues with comparing results between multiple emulators in the case of unusual instructions mean that no tests have been generated for:
1. MOVE [to or from] SR;
2. TRAP;
3. TRAPV;
4. MOVE [to or from] USP;
5. STOP;
6. RTE;
7. Bcc where the offset is an odd number; or
8. BSR where the offset is an odd number.
For both Bcc and BSR, there is good coverage of even-quantity offsets.
## Questionable Results
Values for the undocumented flags of DIVU and DIVS have not yet been verified, due to a lack of documentation.
Values for the undocumented flags of DIVU and DIVS have not yet been verified, due to a lack of documentation.