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Completely prints tests.
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@ -83,6 +83,31 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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std::vector<Cycle> cycles;
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std::vector<Cycle> cycles;
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};
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};
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template <typename Processor> void print_registers(const Processor &processor, int pc_offset) {
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using Register = CPU::MOS6502Esque::Register;
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printf("\"pc\": %d, ", (processor.get_value_of_register(Register::ProgramCounter) + pc_offset) & 65535);
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printf("\"s\": %d, ", processor.get_value_of_register(Register::StackPointer));
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printf("\"p\": %d, ", processor.get_value_of_register(Register::Flags));
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printf("\"a\": %d, ", processor.get_value_of_register(Register::A));
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printf("\"x\": %d, ", processor.get_value_of_register(Register::X));
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printf("\"y\": %d, ", processor.get_value_of_register(Register::Y));
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printf("\"dbr\": %d, ", processor.get_value_of_register(Register::DataBank));
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printf("\"d\": %d, ", processor.get_value_of_register(Register::Direct));
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printf("\"pbr\": %d, ", processor.get_value_of_register(Register::ProgramBank));
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printf("\"e\": %d, ", processor.get_value_of_register(Register::EmulationFlag));
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}
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void print_ram(const std::unordered_map<uint32_t, uint8_t> &data) {
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printf("\"ram\": [");
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bool is_first = true;
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for(const auto &pair: data) {
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if(!is_first) printf(", ");
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is_first = false;
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printf("[%d, %d]", pair.first, pair.second);
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}
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printf("]");
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}
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}
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}
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// MARK: - New test generator.
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// MARK: - New test generator.
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@ -107,6 +132,7 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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const bool is_emulated = operation & 256;
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const bool is_emulated = operation & 256;
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const uint8_t opcode = operation & 255;
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const uint8_t opcode = operation & 255;
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for(int test = 0; test < 1; test++) {
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// Ensure processor's next action is an opcode fetch.
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// Ensure processor's next action is an opcode fetch.
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processor.restart_operation_fetch();
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processor.restart_operation_fetch();
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@ -129,7 +155,10 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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// Establish the opcode.
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// Establish the opcode.
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handler.setup(processor, opcode);
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handler.setup(processor, opcode);
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// TODO: dump current state.
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// Dump initial state.
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printf("{ \"name\": \"%02x %c %d\", ", opcode, is_emulated ? 'e' : 'n', test + 1);
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printf("\"initial\": {");
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print_registers(processor, 0);
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// Run to the second opcode fetch.
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// Run to the second opcode fetch.
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handler.opcodes_remaining = 2;
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handler.opcodes_remaining = 2;
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@ -137,8 +166,58 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandler<uint32_t> {
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processor.run_for(Cycles(100));
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processor.run_for(Cycles(100));
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} catch (const StopException &) {}
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} catch (const StopException &) {}
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// TODO: dump initial and final memory contents, and final state.
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// Dump all inventions as initial memory state.
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printf("");
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print_ram(handler.inventions);
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// Dump final state.
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printf("}, \"final\": {");
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print_registers(processor, -1);
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print_ram(handler.ram);
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printf("}, ");
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// Append cycles.
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printf("\"cycles\": [");
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bool is_first = true;
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for(const auto &cycle: handler.cycles) {
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if(!is_first) printf(",");
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is_first = false;
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bool vda = false;
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bool vpa = false;
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bool vpb = false;
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bool read = false;
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bool wait = false;
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using BusOperation = CPU::MOS6502Esque::BusOperation;
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switch(cycle.operation) {
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case BusOperation::Read: read = vda = true; break;
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case BusOperation::ReadOpcode: read = vda = vpa = true; break;
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case BusOperation::ReadProgram: read = vpa = true; break;
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case BusOperation::ReadVector: read = vpb = true; break;
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case BusOperation::InternalOperationRead: read = true; break;
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case BusOperation::Write: vda = true; break;
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case BusOperation::InternalOperationWrite: break;
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case BusOperation::None:
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case BusOperation::Ready: wait = true; break;
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default:
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assert(false);
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}
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printf("[%d, %d, %c%c%c%c]",
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cycle.address,
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cycle.value,
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vda ? 'd' : '-',
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vpa ? 'p' : '-',
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vpb ? 'v' : '-',
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wait ? '-' : (read ? 'r' : 'w'));
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}
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// Terminate object.
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printf("]},\n");
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}
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}
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}
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}
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}
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