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https://github.com/TomHarte/CLK.git
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Separates state transitions and tests.
This commit is contained in:
Thomas Harte
parent
a9971917f5
commit
0c5bb9626b
@ -83,93 +83,8 @@ void Audio::output() {
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}
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}
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bool Audio::Channel::output() {
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// The following attempts to reproduce the audio state diagram provided in
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// Commodore's Hardware Reference Manual.
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//
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// See big comment at the foot of this file.
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switch(state) {
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case State::Disabled:
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// Test for top loop of Commodore's state diagram,
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// which permits CPU-driven audio output.
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if(has_data && !dma_enabled && !interrupt_pending) {
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state = State::PlayingHigh;
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data_latch = data; // i.e. pbufld1
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has_data = false;
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period_counter = period; // i.e. percntrld
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// TODO: volcntrld (see above).
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// Request an interrupt.
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return true;
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}
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// Test for DMA-style transition.
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if(dma_enabled) {
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state = State::WaitingForDummyDMA;
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period_counter = period; // i.e. percntrld
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length_counter = length; // i.e. lenctrld
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break;
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}
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break;
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case State::WaitingForDummyDMA:
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if(!dma_enabled) {
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state = State::Disabled;
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break;
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}
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if(dma_enabled && has_data) {
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has_data = false;
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state = State::WaitingForDMA;
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if(length == 1) {
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length_counter = length;
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return true;
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}
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break;
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}
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break;
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case State::WaitingForDMA:
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if(!dma_enabled) {
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state = State::Disabled;
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break;
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}
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if(dma_enabled && has_data) {
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data_latch = data;
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has_data = false;
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period_counter = period; // i.e. percntrld
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state = State::PlayingHigh;
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break;
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}
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break;
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case State::PlayingHigh:
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// TODO: penhi (i.e. output high byte).
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-- period_counter;
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// This is a reasonable guess as to the exit condition for this node;
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// Commodore doesn't document.
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if(period_counter == 1) {
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state = State::PlayingLow;
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// TODO: if attach period, reload output buffer.
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}
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break;
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default: break;
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}
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return false;
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}
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/*
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Big spiel on the state machine implemented above:
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Big spiel on the state machine:
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Commodore's Hardware Rerefence Manual provides the audio subsystem's state
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machine, so I've just tried to reimplement it verbatim. It's depicted
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@ -225,7 +140,7 @@ bool Audio::Channel::output() {
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if: AUDxON, and AUDxDAT
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action:
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1. volcntrld, percentrld, pbufid1
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2. if napnav, AUDxDR
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2. if napnav, then AUDxDR
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@ -277,11 +192,11 @@ bool Audio::Channel::output() {
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Definitions:
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AUDxON DMA on "x" indicates channel number (signal from DMACON).
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AUDxON DMA on "x" indicates channel number (signal from DMACON).
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AUDxIP Audio interrupt pending (input to channel from interrupt circuitry).
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AUDxIP Audio interrupt pending (input to channel from interrupt circuitry).
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AUDxIR Audio interrupt request (output from channel to interrupt circuitry)
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AUDxIR Audio interrupt request (output from channel to interrupt circuitry)
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intreq1 Interrupt request that combines with intreq2 to form AUDxIR.
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@ -297,32 +212,204 @@ bool Audio::Channel::output() {
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dmasen Restart request enable.
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percntrld Reload period counter from back-up latch typically written
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by processor with AUDxPER (can also be written by attach mode).
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by processor with AUDxPER (can also be written by attach mode).
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percount Count period counter down one latch.
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percount Count period counter down one latch.
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perfin Period counter finished (value = 1).
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perfin Period counter finished (value = 1).
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lencntrld Reload length counter from back-up latch.
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lencntrld Reload length counter from back-up latch.
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lencount Count length counter down one notch.
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lencount Count length counter down one notch.
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lenfin Length counter finished (value = 1).
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lenfin Length counter finished (value = 1).
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volcntrld Reload volume counter from back-up latch.
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volcntrld Reload volume counter from back-up latch.
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pbufld1 Load output buffer from holding latch written to by AUDxDAT.
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pbufld1 Load output buffer from holding latch written to by AUDxDAT.
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pbufld2 Like pbufld1, but only during 010->011 with attach period.
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pbufld2 Like pbufld1, but only during 010->011 with attach period.
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AUDxAV Attach volume. Send data to volume latch of next channel
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AUDxAV Attach volume. Send data to volume latch of next channel
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instead of to D->A converter.
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AUDxAP Attach period. Send data to period latch of next channel
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AUDxAP Attach period. Send data to period latch of next channel
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instead of to the D->A converter.
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penhi Enable the high 8 bits of data to go to the D->A converter.
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penhi Enable the high 8 bits of data to go to the D->A converter.
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napnav /AUDxAV * /AUDxAP + AUDxAV -- no attach stuff or else attach
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napnav /AUDxAV * /AUDxAP + AUDxAV -- no attach stuff or else attach
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volume. Condition for normal DMA and interrupt requests.
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*/
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//
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// Non-action fallback transition.
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//
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template <
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Audio::Channel::State begin,
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Audio::Channel::State end> bool Audio::Channel::transit() {
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state = end;
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return false;
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}
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//
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// Audio::Channel::State::Disabled
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//
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::Disabled,
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Audio::Channel::State::WaitingForDummyDMA>() {
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state = State::WaitingForDummyDMA;
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period_counter = period; // i.e. percntrld
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length_counter = length; // i.e. lenctrld
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return false;
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}
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::Disabled,
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Audio::Channel::State::PlayingHigh>() {
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state = State::PlayingHigh;
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data_latch = data; // i.e. pbufld1
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has_data = false;
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period_counter = period; // i.e. percntrld
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// TODO: volcntrld (see above).
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// Request an interrupt.
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return true;
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}
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template <> bool Audio::Channel::output<Audio::Channel::State::Disabled>() {
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if(has_data && !dma_enabled && !interrupt_pending) {
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return transit<State::Disabled, State::PlayingHigh>();
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}
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// Test for DMA-style transition.
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if(dma_enabled) {
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return transit<State::Disabled, State::WaitingForDummyDMA>();
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}
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return false;
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}
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//
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// Audio::Channel::State::WaitingForDummyDMA
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//
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::WaitingForDummyDMA,
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Audio::Channel::State::WaitingForDMA>() {
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state = State::WaitingForDMA;
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has_data = false;
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if(length == 1) {
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length_counter = length;
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return true;
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}
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return false;
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}
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template <> bool Audio::Channel::output<Audio::Channel::State::WaitingForDummyDMA>() {
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if(!dma_enabled) {
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return transit<State::WaitingForDummyDMA, State::Disabled>();
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}
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if(dma_enabled && has_data) {
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return transit<State::WaitingForDummyDMA, State::WaitingForDMA>();
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}
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return false;
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}
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//
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// Audio::Channel::State::WaitingForDMA
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//
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template <> bool Audio::Channel::transit<
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Audio::Channel::State::WaitingForDMA,
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Audio::Channel::State::PlayingHigh>() {
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state = State::PlayingHigh;
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data_latch = data;
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has_data = false;
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period_counter = period; // i.e. percntrld
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return false;
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}
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template <> bool Audio::Channel::output<Audio::Channel::State::WaitingForDMA>() {
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if(!dma_enabled) {
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return transit<State::WaitingForDummyDMA, State::Disabled>();
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}
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if(dma_enabled && has_data) {
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return transit<State::WaitingForDummyDMA, State::PlayingHigh>();
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}
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return false;
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}
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//
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// Audio::Channel::State::PlayingHigh
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//
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template <> bool Audio::Channel::output<Audio::Channel::State::PlayingHigh>() {
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-- period_counter;
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// This is a reasonable guess as to the exit condition for this node;
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// Commodore doesn't document.
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if(!period_counter) {
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return transit<State::PlayingHigh, State::PlayingLow>();
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}
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// TODO: penhi (i.e. output high byte).
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return false;
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}
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//
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// Audio::Channel::State::PlayingLow
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//
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template <> bool Audio::Channel::output<Audio::Channel::State::PlayingLow>() {
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-- period_counter;
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const bool dma_and_not_done = dma_enabled && !interrupt_pending;
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if(!period_counter && !dma_and_not_done) {
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return transit<State::PlayingLow, State::Disabled>();
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}
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if(!period_counter && dma_and_not_done) {
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return transit<State::PlayingLow, State::PlayingHigh>();
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}
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// TODO: not penhi (i.e. output low byte).
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return false;
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}
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//
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// Dispatcher
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//
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bool Audio::Channel::output() {
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switch(state) {
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case State::Disabled: return output<State::Disabled>();
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case State::WaitingForDummyDMA: return output<State::WaitingForDummyDMA>();
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case State::WaitingForDMA: return output<State::WaitingForDMA>();
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case State::PlayingHigh: return output<State::PlayingHigh>();
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case State::PlayingLow: return output<State::PlayingLow>();
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default:
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assert(false);
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break;
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}
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return false;
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}
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@ -94,6 +94,8 @@ class Audio: public DMADevice<4> {
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} state = State::Disabled;
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bool output();
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template <State state> bool output();
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template <State begin, State end> bool transit();
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} channels_[4];
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};
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