6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-01-11 08:30:55 +00:00
Code Issues Projects Releases Wiki Activity

Extends to support read/write permissions in apply.

Browse Source
This commit is contained in:
Thomas Harte 2021-07-17 21:09:52 -04:00
parent f7de6f790c
commit 0cfc7f732c
1 changed files with 11 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
Processors/68000/68000.hpp
View File

@ -289,29 +289,32 @@ struct Microcycle {
return ((*address) & 0x00fffffe) >> 1; return ((*address) & 0x00fffffe) >> 1;
} }
static constexpr int PermitRead = (1 << 11);
static constexpr int PermitWrite = (1 << 12);
/*! /*!
Assuming this to be a cycle with a data select active, applies it to @c target, Assuming this to be a cycle with a data select active, applies it to @c target
where 'applies' means: subject to the read_write_mask, where 'applies' means:
* if this is a byte read, reads a single byte from @c target; * if this is a byte read, reads a single byte from @c target;
* if this is a word read, reads a word (in the host platform's endianness) from @c target; and * if this is a word read, reads a word (in the host platform's endianness) from @c target; and
* if this is a write, does the converse of a read. * if this is a write, does the converse of a read.
*/ */
forceinline void apply(uint8_t *target) const { forceinline void apply(uint8_t *target, int read_write_mask = PermitRead | PermitWrite) const {
switch(operation & (SelectWord | SelectByte | Read)) { switch((operation | read_write_mask) & (SelectWord | SelectByte | Read | PermitRead | PermitWrite)) {
default: default:
break; break;
case SelectWord | Read: case SelectWord | Read | PermitRead:
value->full = *reinterpret_cast<uint16_t *>(target); value->full = *reinterpret_cast<uint16_t *>(target);
break; break;
case SelectByte | Read: case SelectByte | Read | PermitRead:
value->halves.low = *target; value->halves.low = *target;
break; break;
case Microcycle::SelectWord: case SelectWord | PermitWrite:
*reinterpret_cast<uint16_t *>(target) = value->full; *reinterpret_cast<uint16_t *>(target) = value->full;
break; break;
case Microcycle::SelectByte: case SelectByte | PermitWrite:
*target = value->halves.low; *target = value->halves.low;
break; break;
} }