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Seeking proper [F/D]DCB emulation: the offset comes before the final byte of opcode, and adding seems to overlap with the opcode fetch, which does not increment R. Also needs to duplicate the result to visible registers.
This commit is contained in:
Thomas Harte
parent
98423c6e41
commit
0d2d04e17b
@ -169,19 +169,18 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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uint8_t sign_result_, zero_result_, bit5_result_, half_carry_flag_, bit3_result_, parity_overflow_flag_, subtract_flag_, carry_flag_;
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int number_of_cycles_;
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const MicroOp **program_table_;
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uint8_t operation_;
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RegisterPair temp16_;
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uint8_t temp8_;
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MicroOp *fetch_decode_execute_;
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MicroOp **current_instruction_page_;
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struct InstructionPage {
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MicroOp *instructions[256];
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MicroOp *all_operations;
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bool increments_r;
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InstructionPage() : all_operations(nullptr) {
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InstructionPage() : all_operations(nullptr), increments_r(true) {
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for(int c = 0; c < 256; c++) {
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instructions[c] = nullptr;
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}
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@ -191,6 +190,8 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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delete[] all_operations;
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}
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};
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InstructionPage *current_instruction_page_;
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InstructionPage base_page_;
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InstructionPage ed_page_;
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InstructionPage fd_page_;
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@ -203,6 +204,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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#define XX {MicroOp::None, 0}
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#define INDEX() {MicroOp::IndexedPlaceHolder}, FETCH(temp8_, pc_), WAIT(5), {MicroOp::CalculateIndexAddress, &index}
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#define FINDEX() {MicroOp::IndexedPlaceHolder}, FETCH(temp8_, pc_), {MicroOp::CalculateIndexAddress, &index}
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#define INDEX_ADDR() (add_offsets ? temp16_ : index)
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/// Fetches into x from address y, and then increments y.
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@ -244,13 +246,26 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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Program(INDEX(), FETCHL(temp8_, INDEX_ADDR()), {MicroOp::op, &temp8_}), \
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Program({MicroOp::op, &a_})
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#define RMW(x, op, ...) Program(INDEX(), FETCHL(x, INDEX_ADDR()), {MicroOp::op, &x}, WAIT(1), STOREL(x, INDEX_ADDR()))
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#define RMWI(x, op, ...) Program(WAIT(1), FETCHL(x, INDEX_ADDR()), {MicroOp::op, &x}, WAIT(1), STOREL(x, INDEX_ADDR()))
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#define MODIFY_OP_GROUP(op) \
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Program({MicroOp::op, &bc_.bytes.high}), Program({MicroOp::op, &bc_.bytes.low}), \
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Program({MicroOp::op, &de_.bytes.high}), Program({MicroOp::op, &de_.bytes.low}), \
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Program({MicroOp::op, &index.bytes.high}), Program({MicroOp::op, &index.bytes.low}), \
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Program(INDEX(), FETCHL(temp8_, INDEX_ADDR()), {MicroOp::op, &temp8_}, WAIT(1), STOREL(temp8_, INDEX_ADDR())), \
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RMW(temp8_, op), \
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Program({MicroOp::op, &a_})
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#define MUTATE_OP_GROUP(op) \
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RMWI(bc_.bytes.high, op), \
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RMWI(bc_.bytes.low, op), \
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RMWI(de_.bytes.high, op), \
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RMWI(de_.bytes.low, op), \
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RMWI(hl_.bytes.high, op), \
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RMWI(hl_.bytes.low, op), \
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RMWI(temp8_, op), \
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RMWI(a_, op)
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#define ADD16(d, s) Program(WAIT(4), WAIT(3), {MicroOp::ADD16, &s.full, &d.full})
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#define ADC16(d, s) Program(WAIT(4), WAIT(3), {MicroOp::ADC16, &s.full, &d.full})
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@ -283,11 +298,14 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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target.instructions[c] = &target.all_operations[destination];
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for(int t = 0; t < lengths[c];) {
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// If an index placeholder is hit then drop it, and if offsets aren't being added,
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// then also drop the indexing that follows and which is assumed here to be four
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// micro-ops in length. Coupled to the INDEX() macro.
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// then also drop the indexing that follows, which is assumed to be everything
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// up to and including the next ::CalculateIndexAddress. Coupled to the INDEX() macro.
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if(table[c][t].type == MicroOp::IndexedPlaceHolder) {
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t++;
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if(!add_offsets) t += 4;
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if(!add_offsets) {
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while(table[c][t].type != MicroOp::CalculateIndexAddress) t++;
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t++;
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}
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}
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target.all_operations[destination] = table[c][t];
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destination++;
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@ -361,42 +379,30 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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}
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void assemble_cb_page(InstructionPage &target, RegisterPair &index, bool add_offsets) {
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#define OCTO_OP_GROUP(x) MODIFY_OP_GROUP(x), MODIFY_OP_GROUP(x), MODIFY_OP_GROUP(x), MODIFY_OP_GROUP(x), MODIFY_OP_GROUP(x), MODIFY_OP_GROUP(x), MODIFY_OP_GROUP(x), MODIFY_OP_GROUP(x)
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#define OCTO_OP_GROUP(m, x) m(x), m(x), m(x), m(x), m(x), m(x), m(x), m(x)
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#define CB_PAGE(m) m(RLC), m(RRC), m(RL), m(RR), m(SLA), m(SRA), m(SLL), m(SRL), OCTO_OP_GROUP(m, BIT), OCTO_OP_GROUP(m, RES), OCTO_OP_GROUP(m, SET)
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InstructionTable cb_program_table = {
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/* 0x00 RLC B; 0x01 RLC C; 0x02 RLC D; 0x03 RLC E; 0x04 RLC H; 0x05 RLC L; 0x06 RLC (HL); 0x07 RLC A */
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MODIFY_OP_GROUP(RLC),
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/* 0x08 RRC B; 0x09 RRC C; 0x0a RRC D; 0x0b RRC E; 0x0c RRC H; 0x0d RRC L; 0x0e RRC (HL); 0x0f RRC A */
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MODIFY_OP_GROUP(RRC),
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/* 0x10 RL B; 0x11 RL C; 0x12 RL D; 0x13 RL E; 0x14 RL H; 0x15 RL L; 0x16 RL (HL); 0x17 RL A */
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MODIFY_OP_GROUP(RL),
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/* 0x18 RR B; 0x99 RR C; 0x1a RR D; 0x1b RR E; 0x1c RR H; 0x1d RR L; 0x1e RR (HL); 0x1f RR A */
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MODIFY_OP_GROUP(RR),
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/* 0x20 SLA B; 0x21 SLA C; 0x22 SLA D; 0x23 SLA E; 0x24 SLA H; 0x25 SLA L; 0x26 SLA (HL); 0x27 SLA A */
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MODIFY_OP_GROUP(SLA),
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/* 0x28 SRA B; 0x29 SRA C; 0x2a SRA D; 0x2b SRA E; 0x2c SRA H; 0x2d SRA L; 0x2e SRA (HL); 0x2f SRA A */
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MODIFY_OP_GROUP(SRA),
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/* 0x30 SLL B; 0x31 SLL C; 0x32 SLL D; 0x33 SLL E; 0x34 SLL H; 0x35 SLL L; 0x36 SLL (HL); 0x37 SLL A */
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MODIFY_OP_GROUP(SLL),
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/* 0x38 SRL B; 0x39 SRL C; 0x3a SRL D; 0x3b SRL E; 0x3c SRL H; 0x3d SRL L; 0x3e SRL (HL); 0x3f SRL A */
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MODIFY_OP_GROUP(SRL),
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/* 0x40 – 0x7f: BIT */
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OCTO_OP_GROUP(BIT),
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/* 0x80 – 0xcf: RES */
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OCTO_OP_GROUP(RES),
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/* 0xd0 – 0xdf: SET */
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OCTO_OP_GROUP(SET)
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CB_PAGE(MODIFY_OP_GROUP)
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};
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assemble_page(target, cb_program_table, add_offsets);
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InstructionTable offsets_cb_program_table = {
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CB_PAGE(MUTATE_OP_GROUP)
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};
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assemble_page(target, add_offsets ? offsets_cb_program_table : cb_program_table, add_offsets);
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#undef OCTO_OP_GROUP
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#undef CB_PAGE
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}
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void assemble_base_page(InstructionPage &target, RegisterPair &index, bool add_offsets, InstructionPage &cb_page) {
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@ -533,7 +539,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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/* 0xc6 ADD A, n */ Program(FETCH(temp8_, pc_), {MicroOp::ADD8, &temp8_}),
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/* 0xc7 RST 00h */ RST(),
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/* 0xc8 RET Z */ RET(TestZ), /* 0xc9 RET */ Program(POP(pc_)),
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/* 0xca JP Z */ JP(TestZ), /* 0xcb [CB page] */Program({MicroOp::SetInstructionPage, &cb_page}),
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/* 0xca JP Z */ JP(TestZ), /* 0xcb [CB page] */Program({MicroOp::SetInstructionPage, &cb_page}, FINDEX()),
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/* 0xcc CALL Z */ CALL(TestZ), /* 0xcd CALL */ Program(FETCH16(temp16_, pc_), WAIT(1), PUSH(pc_), {MicroOp::Move16, &temp16_.full, &pc_.full}),
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/* 0xce ADC A, n */ Program(FETCH(temp8_, pc_), {MicroOp::ADC8, &temp8_}),
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/* 0xcf RST 08h */ RST(),
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@ -587,12 +593,12 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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}
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void decode_operation(uint8_t operation) {
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if(current_instruction_page_[operation]->type == MicroOp::None) {
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if(current_instruction_page_->instructions[operation]->type == MicroOp::None) {
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uint8_t page = 0x00;
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if(current_instruction_page_ == ed_page_.instructions) page = 0xed;
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if(current_instruction_page_ == fd_page_.instructions) page = 0xfd;
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if(current_instruction_page_ == &ed_page_) page = 0xed;
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if(current_instruction_page_ == &fd_page_) page = 0xfd;
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printf("Unknown Z80 operation %02x %02x!!!\n", page, operation);
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} else schedule_program(current_instruction_page_[operation]);
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} else schedule_program(current_instruction_page_->instructions[operation]);
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}
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public:
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@ -602,6 +608,9 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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assemble_base_page(fd_page_, iy_, true, fdcb_page_);
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assemble_ed_page(ed_page_);
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assemble_fetch_decode_execute();
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fdcb_page_.increments_r = false;
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ddcb_page_.increments_r = false;
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}
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~Processor() {
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delete[] fetch_decode_execute_;
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@ -620,7 +629,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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#define checkSchedule() \
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if(!scheduled_programs_[schedule_programs_read_pointer_]) {\
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current_instruction_page_ = base_page_.instructions;\
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current_instruction_page_ = &base_page_;\
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schedule_program(fetch_decode_execute_);\
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}
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@ -649,8 +658,8 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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checkSchedule();
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break;
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case MicroOp::DecodeOperation:
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if(current_instruction_page_->increments_r) r_ = (r_ & 0x80) | ((r_ + 1) & 0x7f);
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pc_.full++;
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r_ = (r_ & 0x80) | ((r_ + 1) & 0x7f);
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decode_operation(operation_);
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break;
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@ -1171,7 +1180,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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case MicroOp::SetInstructionPage:
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schedule_program(fetch_decode_execute_);
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current_instruction_page_ = ((InstructionPage *)operation->source)->instructions;
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current_instruction_page_ = (InstructionPage *)operation->source;
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// printf("+ ");
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break;
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