6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-22 12:33:29 +00:00
Code Issues Projects Releases Wiki Activity

Corrects delay for SN access.

Browse Source
This commit is contained in:
Thomas Harte 2019-02-27 22:58:43 -05:00
parent 56e691f256
commit 0dbd8a667d
1 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
Machines/ColecoVision/ColecoVision.cpp
View File

@ -191,12 +191,13 @@ class ConcreteMachine:
// MARK: Z80::BusHandler
forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
// The SN76489 will use its ready line to trigger the Z80's wait for three
// cycles when accessed. M1 cycles are extended by a single cycle. Short-circuit
// that whole piece of communications by just accruing the time here if applicable.
// The SN76489 will use its ready line to trigger the Z80's wait, which will add
// thirty-one (!) cycles when accessed. M1 cycles are extended by a single cycle.
// This code works out the delay up front in order to simplify execution flow, though
// technically this is a little duplicative.
HalfCycles penalty(0);
if(cycle.operation == CPU::Z80::PartialMachineCycle::Output && ((*cycle.address >> 5) & 7) == 7) {
penalty = HalfCycles(6);
if((cycle.operation == CPU::Z80::PartialMachineCycle::Output || cycle.operation == CPU::Z80::PartialMachineCycle::Input) && ((*cycle.address >> 5) & 7) == 7) {
penalty = HalfCycles(62);
} else if(cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) {
penalty = HalfCycles(2);
}