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Interrupt fixes: supply proper address, raise level, fetch from vector.
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@ -425,6 +425,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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captured_status_.w = status_.status();
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status_.is_supervisor = true;
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status_.trace_flag = 0;
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status_.interrupt_level = captured_interrupt_level_;
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did_update_status();
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// Prepare for stack activity.
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@ -436,7 +437,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Access(captured_status_); // ns
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// Do the interrupt cycle, to obtain a vector.
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temporary_address_.l = uint32_t(captured_interrupt_level_);
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temporary_address_.l = 0xffff'fff8 | uint32_t(captured_interrupt_level_);
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SetupDataAccess(0, Microcycle::InterruptAcknowledge);
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SetDataAddress(temporary_address_.l);
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Access(temporary_value_.low); // ni
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@ -462,7 +463,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
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SetDataAddress(temporary_address_.l);
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temporary_address_.l <<= 2;
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temporary_address_.l = uint32_t(temporary_value_.w << 2);
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Access(program_counter_.high); // nV
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temporary_address_.l += 2;
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@ -2279,7 +2280,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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#define TODOState(x) \
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BeginState(x): [[fallthrough]];
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TODOState(BusOrAddressErrorException);
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BeginState(BusOrAddressErrorException):
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assert(false);
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MoveToStateSpecific(Decode);
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#undef TODOState
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