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https://github.com/TomHarte/CLK.git
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Further rounds out decoder.
This commit is contained in:
Thomas Harte
parent
d318ab4e70
commit
0ef42f93ff
@ -10,18 +10,6 @@
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using namespace CPU::Decoder::PowerPC;
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// Unmapped:
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//
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// absx, clcs, divx, divsx, dozx, dozi, lscbxx, maskgx, maskirx, mulx,
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// nabsx, rlmix, rribx, slex, sleqx, sliqx, slliqx, sllqx, slqx,
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// sraiqx, sraqx, srex, sreax, sreqx, sriqx, srliqx, srlqx, srqx,
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//
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// stwcx_,
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//
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// frsqrtsx,
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//
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// extswx,
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Decoder::Decoder(Model model) : model_(model) {}
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Instruction Decoder::decode(uint32_t opcode) {
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@ -37,6 +25,12 @@ Instruction Decoder::decode(uint32_t opcode) {
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// it as a 9-bit field with a flag at the top.
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//
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// I've decided to hew directly to the mnemonics.
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//
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// Various opcodes in the 1995 documentation define reserved bits,
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// which are given the nominal value of 0. It does not give a formal
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// definition of a reserved bit. As a result this code does not
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// currently check the value of reserved bits. That may need to change
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// if/when I add support for extended instruction sets.
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#define Bind(mask, operation) case mask: return Instruction(Operation::operation, opcode);
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#define BindSupervisor(mask, operation) case mask: return Instruction(Operation::operation, opcode, true);
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@ -50,7 +44,7 @@ Instruction Decoder::decode(uint32_t opcode) {
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return Instruction(opcode);
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#define Six(x) (unsigned(x) << 26)
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#define SixTen(x, y) (Six(x) | (y << 1))
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#define SixTen(x, y) (Six(x) | ((y) << 1))
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// First pass: weed out all those instructions identified entirely by the
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// top six bits.
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@ -86,36 +80,69 @@ Instruction Decoder::decode(uint32_t opcode) {
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Bind(Six(0b110100), stfs); Bind(Six(0b110101), stfsu);
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Bind(Six(0b110110), stfd); Bind(Six(0b110111), stfdu);
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// Assumed below here: reserved bits can be ignored.
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// This might need to be a function of CPU model.
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BindConditional(is601, Six(9), dozi);
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BindConditional(is601, Six(22), rlmix);
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Bind(Six(0b001010), cmpli); Bind(Six(0b001011), cmpi);
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}
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// Second pass: all those with a top six bits and a bottom nine or ten.
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switch(opcode & SixTen(0b111111, 0b1111111111)) {
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default: break;
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BindConditional(is64bit, SixTen(0b011111, 0b0000001001), mulhdux);
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// 64-bit instructions.
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BindConditional(is64bit, SixTen(0b011111, 0b0000001001), mulhdux); BindConditional(is64bit, SixTen(0b011111, 0b1000001001), mulhdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0000010101), ldx);
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BindConditional(is64bit, SixTen(0b011111, 0b0000011011), sldx);
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BindConditional(is64bit, SixTen(0b011111, 0b0000110101), ldux);
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BindConditional(is64bit, SixTen(0b011111, 0b0000111010), cntlzdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0001000100), td);
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BindConditional(is64bit, SixTen(0b011111, 0b0001001001), mulhdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0001001001), mulhdx); BindConditional(is64bit, SixTen(0b011111, 0b1001001001), mulhdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0001010100), ldarx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010010101), stdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010110101), stdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0011101001), mulld); BindConditional(is64bit, SixTen(0b011111, 0b1011101001), mulld);
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BindConditional(is64bit, SixTen(0b011111, 0b0101010101), lwax);
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BindConditional(is64bit, SixTen(0b011111, 0b0101110101), lwaux);
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// BindConditional(is64bit, SixTen(0b011111, 0b1100111011), sradix); // TODO: encoding is unclear re: the sh flag.
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BindConditional(is64bit, SixTen(0b011111, 0b1100111011), sradix); BindConditional(is64bit, SixTen(0b011111, 0b1100111010), sradix);
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BindConditional(is64bit, SixTen(0b011111, 0b0110110010), slbie);
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BindConditional(is64bit, SixTen(0b011111, 0b0111001001), divdux); BindConditional(is64bit, SixTen(0b011111, 0b1111001001), divdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0111101001), divdx); BindConditional(is64bit, SixTen(0b011111, 0b1111101001), divdx);
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BindConditional(is64bit, SixTen(0b011111, 0b1000011011), srdx);
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BindConditional(is64bit, SixTen(0b011111, 0b1100011010), sradx);
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BindConditional(is64bit, SixTen(0b011111, 0b1111011010), extsw);
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BindConditional(is64bit, SixTen(0b111111, 0b1111011010), extsw);
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// Power instructions; these are all taken from the MPC601 manual rather than
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// the PowerPC Programmer's Reference Guide, hence the decimal encoding of the
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// ten-bit field.
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BindConditional(is601, SixTen(0b011111, 360), absx); BindConditional(is601, SixTen(0b011111, 512 + 360), absx);
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BindConditional(is601, SixTen(0b011111, 531), clcs);
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BindConditional(is601, SixTen(0b011111, 331), divx); BindConditional(is601, SixTen(0b011111, 512 + 331), divx);
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BindConditional(is601, SixTen(0b011111, 363), divsx); BindConditional(is601, SixTen(0b011111, 512 + 363), divsx);
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BindConditional(is601, SixTen(0b011111, 264), dozx); BindConditional(is601, SixTen(0b011111, 512 + 264), dozx);
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BindConditional(is601, SixTen(0b011111, 277), lscbxx);
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BindConditional(is601, SixTen(0b011111, 29), maskgx);
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BindConditional(is601, SixTen(0b011111, 541), maskirx);
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BindConditional(is601, SixTen(0b011111, 107), mulx); BindConditional(is601, SixTen(0b011111, 512 + 107), mulx);
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BindConditional(is601, SixTen(0b011111, 488), nabsx); BindConditional(is601, SixTen(0b011111, 512 + 488), nabsx);
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BindConditional(is601, SixTen(0b011111, 537), rribx);
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BindConditional(is601, SixTen(0b011111, 153), slex);
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BindConditional(is601, SixTen(0b011111, 217), sleqx);
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BindConditional(is601, SixTen(0b011111, 184), sliqx);
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BindConditional(is601, SixTen(0b011111, 248), slliqx);
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BindConditional(is601, SixTen(0b011111, 216), sllqx);
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BindConditional(is601, SixTen(0b011111, 152), slqx);
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BindConditional(is601, SixTen(0b011111, 952), sraiqx);
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BindConditional(is601, SixTen(0b011111, 920), sraqx);
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BindConditional(is601, SixTen(0b011111, 665), srex);
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BindConditional(is601, SixTen(0b011111, 921), sreax);
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BindConditional(is601, SixTen(0b011111, 729), sreqx);
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BindConditional(is601, SixTen(0b011111, 696), sriqx);
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BindConditional(is601, SixTen(0b011111, 760), srliqx);
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BindConditional(is601, SixTen(0b011111, 728), srlqx);
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BindConditional(is601, SixTen(0b011111, 664), srqx);
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// 32-bit instructions.
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Bind(SixTen(0b010011, 0b0000000000), mcrf);
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Bind(SixTen(0b010011, 0b0000010000), bclrx);
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Bind(SixTen(0b010011, 0b0000100001), crnor);
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@ -133,7 +160,7 @@ Instruction Decoder::decode(uint32_t opcode) {
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Bind(SixTen(0b011111, 0b0000000100), tw);
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Bind(SixTen(0b011111, 0b0000001000), subfcx); Bind(SixTen(0b011111, 0b1000001000), subfcx);
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Bind(SixTen(0b011111, 0b0000001010), addcx); Bind(SixTen(0b011111, 0b1000001010), addcx);
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Bind(SixTen(0b011111, 0b0000001011), mulhwux);
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Bind(SixTen(0b011111, 0b0000001011), mulhwux); Bind(SixTen(0b011111, 0b1000001011), mulhwux);
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Bind(SixTen(0b011111, 0b0000010011), mfcr);
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Bind(SixTen(0b011111, 0b0000010100), lwarx);
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Bind(SixTen(0b011111, 0b0000010111), lwzx);
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@ -145,7 +172,7 @@ Instruction Decoder::decode(uint32_t opcode) {
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Bind(SixTen(0b011111, 0b0000110110), dcbst);
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Bind(SixTen(0b011111, 0b0000110111), lwzux);
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Bind(SixTen(0b011111, 0b0000111100), andcx);
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Bind(SixTen(0b011111, 0b0001001011), mulhwx);
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Bind(SixTen(0b011111, 0b0001001011), mulhwx); Bind(SixTen(0b011111, 0b1001001011), mulhwx);
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Bind(SixTen(0b011111, 0b0001010011), mfmsr);
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Bind(SixTen(0b011111, 0b0001010110), dcbf);
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Bind(SixTen(0b011111, 0b0001010111), lbzx);
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@ -279,10 +306,22 @@ Instruction Decoder::decode(uint32_t opcode) {
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Bind(SixTen(0b111111, 0b11010), frsqrtex);
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}
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// TODO: stwcx., stdcx. stwcx_
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// stwcx. and stdcx.
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switch(opcode & 0b111111'00'00000000'000'111111111'1){
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case 0b011111'00'00000000'00000'0010010110'1: return Instruction(Operation::stwcx_, opcode);
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case 0b011111'00'00000000'00000'0011010110'1:
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if(is64bit()) return Instruction(Operation::stdcx_, opcode);
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return Instruction(opcode);
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}
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// Check for sc.
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if((opcode & 0b010001'00000'00000'00000000000000'1'0) == 0b010001'00000'00000'00000000000000'1'0) {
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// std and stdu
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switch(opcode & 0b111111'00'00000000'00000000'000000'11){
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case 0b111110'00'00000000'00000000'000000'00: return Instruction(Operation::std, opcode);
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case 0b111110'00'00000000'00000000'000000'01: return Instruction(Operation::stdu, opcode);
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}
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// sc
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if((opcode & 0b111111'00'00000000'00000000'000000'1'0) == 0b010001'00'00000000'00000000'000000'1'0) {
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return Instruction(Operation::sc, opcode);
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}
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@ -9,6 +9,7 @@
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#ifndef PowerPC_hpp
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#define PowerPC_hpp
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#include <cstddef>
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#include <cstdint>
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namespace CPU {
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@ -54,12 +55,12 @@ enum class Operation: uint8_t {
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tlbia, tlbie, tlbsync,
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// Optional.
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fresx, frsqrtex, fselx, fsqrtx, frsqrtsx, slbia, slbie, stfiwx,
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fresx, frsqrtex, fselx, fsqrtx, slbia, slbie, stfiwx,
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// 64-bit only PowerPC instructions.
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cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx, tdi, mulhdux,
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ldx, sldx, ldux, td, mulhdx, ldarx, stdx, stdux, mulld, lwax, lwaux,
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sradix, srdx, sradx, extsw, fsqrtsx
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sradix, srdx, sradx, extsw, fsqrtsx, std, stdu, stdcx_,
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};
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/*!
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@ -73,40 +74,98 @@ struct Instruction {
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const bool is_supervisor = false;
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const uint32_t opcode = 0;
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// PowerPC uses a fixed-size instruction word.
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size_t size() {
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return 4;
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}
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Instruction(uint32_t opcode) : opcode(opcode) {}
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Instruction(Operation operation, uint32_t opcode, bool is_supervisor = false) : operation(operation), is_supervisor(is_supervisor), opcode(opcode) {}
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// Instruction fields are decoded below; naming is as directly dictated by
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// Motorola's documentation, and the definitions below are sorted by synonym.
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// Instruction fields are decoded below; naming is a compromise between
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// Motorola's documentation and IBM's.
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//
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// I've dutifully implemented various synonyms with unique entry points,
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// in order to capture that information here rather than thrusting it upon
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// the reader of whatever implementation may follow.
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// TODO: d, ds, FM, MB, ME, NB, OPCD, SH, SR, XO
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/// Immediate field used to specify an unsigned 16-bit integer.
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uint16_t uimm() { return uint16_t(opcode & 0xffff); }
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/// Immediate field used to specify a signed 16-bit integer.
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int16_t simm() { return int16_t(opcode & 0xffff); }
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/// Immediate field used as data to be placed into a field in the floating point status and condition register.
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int32_t imm() { return (opcode >> 12) & 0xf; }
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int to() { return (opcode >> 21) & 0x1f; }
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int d() { return (opcode >> 21) & 0x1f; }
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int bo() { return (opcode >> 21) & 0x1f; }
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int crbD() { return (opcode >> 21) & 0x1f; }
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int s() { return (opcode >> 21) & 0x1f; }
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/// Specifies the conditions on which to trap.
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int32_t to() { return (opcode >> 21) & 0x1f; }
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int a() { return (opcode >> 16) & 0x1f; }
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int bi() { return (opcode >> 16) & 0x1f; }
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int crbA() { return (opcode >> 16) & 0x1f; }
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/// Register source A or destination.
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uint32_t rA() { return (opcode >> 16) & 0x1f; }
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/// Register source B.
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uint32_t rB() { return (opcode >> 11) & 0x1f; }
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/// Register destination.
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uint32_t rD() { return (opcode >> 21) & 0x1f; }
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/// Register source.
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uint32_t rS() { return (opcode >> 21) & 0x1f; }
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int b() { return (opcode >> 11) & 0x1f; }
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int crbB() { return (opcode >> 11) & 0x1f; }
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/// Floating point register source A.
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uint32_t frA() { return (opcode >> 16) & 0x1f; }
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/// Floating point register source B.
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uint32_t frB() { return (opcode >> 11) & 0x1f; }
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/// Floating point register source C.
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uint32_t frC() { return (opcode >> 6) & 0x1f; }
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/// Floating point register source.
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uint32_t frS() { return (opcode >> 21) & 0x1f; }
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/// Floating point register destination.
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uint32_t frD() { return (opcode >> 21) & 0x1f; }
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int c() { return (opcode >> 6) & 0x1f; }
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/// Branch conditional options.
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uint32_t bo() { return (opcode >> 21) & 0x1f; }
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/// Source condition register bit for branch conditionals.
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uint32_t bi() { return (opcode >> 16) & 0x1f; }
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/// Branch displacement; provided as already sign extended.
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int16_t bd() { return int16_t(opcode & 0xfffc); }
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int crfd() { return (opcode >> 23) & 0x07; }
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int bd() { return (opcode >> 2) & 0x3fff; }
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int li() { return (opcode >> 2) & 0x0fff; }
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/// Condition register source bit A.
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uint32_t crbA() { return (opcode >> 16) & 0x1f; }
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/// Condition register source bit B.
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uint32_t crbB() { return (opcode >> 11) & 0x1f; }
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/// Condition register (or floating point status & condition register) destination bit.
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uint32_t crbD() { return (opcode >> 21) & 0x1f; }
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// Various single bit fields.
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int l() { return (opcode >> 21) & 0x01; }
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int aa() { return (opcode >> 1) & 0x01; }
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int lk() { return opcode & 0x01; }
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int rc() { return opcode & 0x01; }
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/// Condition register (or floating point status & condition register) destination field.
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uint32_t crfD() { return (opcode >> 23) & 0x07; }
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/// Condition register (or floating point status & condition register) source field.
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uint32_t crfS() { return (opcode >> 18) & 0x07; }
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/// Mask identifying fields to be updated by mtcrf.
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uint32_t crm() { return (opcode >> 12) & 0xff; }
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/// Mask identifying fields to be updated by mtfsf.
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uint32_t fm() { return (opcode >> 17) & 0xff; }
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/// A 24-bit signed number; provided as already sign extended.
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int32_t li() {
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constexpr uint32_t extensions[2] = {
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0x0000'0000,
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0xfc00'0000
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};
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const uint32_t value = (opcode & 0x3fff'fffc) | extensions[(opcode >> 26) & 1];
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return int32_t(value);
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}
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/// Absolute address bit; @c 0 or @c non-0.
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uint32_t aa() { return opcode & 0x02; }
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/// Link bit; @c 0 or @c non-0.
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uint32_t lk() { return opcode & 0x01; }
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/// Record bit; @c 0 or @c non-0.
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uint32_t rc() { return opcode & 0x01; }
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/// Whether to compare 32-bit or 64-bit numbers [for 64-bit implementations only]; @c 0 or @c non-0.
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uint32_t l() { return opcode & 0x200000; }
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/// Enables setting of OV and SO in the XER; @c 0 or @c non-0.
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uint32_t oe() { return opcode & 0x800; }
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};
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struct Decoder {
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