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Attempt to honour the trace flag.

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This commit is contained in:
Thomas Harte 2022-05-24 15:47:47 -04:00
parent 01e93ba916
commit 0f7cb2fa5a
2 changed files with 16 additions and 2 deletions
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15
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -17,8 +17,6 @@
namespace CPU { namespace CPU {
namespace MC68000Mk2 { namespace MC68000Mk2 {
// TODO: obeyance of the trace flag.
/// States for the state machine which are named by /// States for the state machine which are named by
/// me for their purpose rather than automatically by file position. /// me for their purpose rather than automatically by file position.
/// These are negative to avoid ambiguity with the other group. /// These are negative to avoid ambiguity with the other group.
@ -351,6 +349,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
status_.is_supervisor = true; status_.is_supervisor = true;
status_.interrupt_level = 7; status_.interrupt_level = 7;
status_.trace_flag = 0; status_.trace_flag = 0;
should_trace_ = 0;
did_update_status(); did_update_status();
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord); SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
@ -381,6 +380,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
status_.is_supervisor = true; status_.is_supervisor = true;
status_.trace_flag = 0; status_.trace_flag = 0;
status_.interrupt_level = 7; status_.interrupt_level = 7;
should_trace_ = 0;
did_update_status(); did_update_status();
SetupDataAccess(0, Microcycle::SelectWord); SetupDataAccess(0, Microcycle::SelectWord);
@ -450,6 +450,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
status_.is_supervisor = true; status_.is_supervisor = true;
status_.trace_flag = 0; status_.trace_flag = 0;
status_.interrupt_level = 7; status_.interrupt_level = 7;
should_trace_ = 0;
did_update_status(); did_update_status();
SetupDataAccess(0, Microcycle::SelectWord); SetupDataAccess(0, Microcycle::SelectWord);
@ -510,6 +511,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
status_.is_supervisor = true; status_.is_supervisor = true;
status_.trace_flag = 0; status_.trace_flag = 0;
status_.interrupt_level = captured_interrupt_level_; status_.interrupt_level = captured_interrupt_level_;
should_trace_ = 0;
did_update_status(); did_update_status();
// Prepare for stack activity. // Prepare for stack activity.
@ -572,6 +574,15 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
MoveToStateSpecific(DoInterrupt); MoveToStateSpecific(DoInterrupt);
} }
// Potentially perform a trace.
if(should_trace_) {
exception_vector_ = InstructionSet::M68k::Exception::Trace;
MoveToStateSpecific(StandardException);
}
// Capture the current trace flag.
should_trace_ = status_.trace_flag;
// Read and decode an opcode. // Read and decode an opcode.
opcode_ = prefetch_.high.w; opcode_ = prefetch_.high.w;
instruction_ = decoder_.decode(opcode_); instruction_ = decoder_.decode(opcode_);

3
Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
View File

@ -58,6 +58,9 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
/// Current input interrupt level. /// Current input interrupt level.
int bus_interrupt_level_ = 0; int bus_interrupt_level_ = 0;
// Whether to trace at the end of this instruction.
InstructionSet::M68k::Status::FlagT should_trace_ = 0;
// I don't have great information on the 68000 interrupt latency; as a first // I don't have great information on the 68000 interrupt latency; as a first
// guess, capture the bus interrupt level upon every prefetch, and use that for // guess, capture the bus interrupt level upon every prefetch, and use that for
// the inner-loop decision. // the inner-loop decision.