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Merge pull request #1404 from TomHarte/65816SquareD

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65816: correct emulation-mode `[d], y`, `PEI` and `PLB`.
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Thomas Harte 2024-09-21 21:46:00 -04:00 committed by GitHub
commit 10f8318e79
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2 changed files with 21 additions and 8 deletions
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13
ClockReceiver/ClockReceiver.hpp
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@ -140,6 +140,19 @@ template <class T> class WrappedInt {
/// @returns The underlying int, converted to an integral type of your choosing, clamped to that int's range.
template<typename Type = IntType> forceinline constexpr Type as() const {
if constexpr (sizeof(Type) == sizeof(IntType)) {
if constexpr (std::is_same_v<Type, IntType>) {
return length_;
} else if constexpr (std::is_signed_v<Type>) {
// Both integers are the same size, but a signed result is being asked for
// from an unsigned original.
return length_ > Type(std::numeric_limits<Type>::max()) ? Type(std::numeric_limits<Type>::max()) : Type(length_);
} else {
// An unsigned result is being asked for from a signed original.
return length_ < 0 ? 0 : Type(length_);
}
}
const auto clamped = std::clamp(length_, IntType(std::numeric_limits<Type>::min()), IntType(std::numeric_limits<Type>::max()));
return Type(clamped);
}

16
Processors/65816/Implementation/65816Storage.cpp
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@ -493,7 +493,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
static void direct_indirect_indexed_long(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
target(CycleFetchIncrementPC); // DO.
target(OperationConstructDirect);
target(OperationConstructDirectLong);
target(CycleFetchPreviousPCThrowaway); // IO.
target(CycleFetchIncrementData); // AAL.
@ -667,13 +667,13 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(OperationPerform);
}
// 22b(ii). Stack; s, PLx, ignoring emulation mode. I.e. PLD.
static void stack_pld(AccessType, bool, const std::function<void(MicroOp)> &target) {
// 22b(ii). Stack; s, PLx, ignoring emulation mode. I.e. PLD and PLB.
static void stack_pld_plb(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
target(CycleFetchPCThrowaway); // IO.
target(CycleFetchPCThrowaway); // IO.
target(CyclePullNotEmulation); // REG low.
target(CyclePullNotEmulation); // REG [high].
if(!is8bit) target(CyclePullNotEmulation); // REG low.
target(CyclePullNotEmulation); // REG [high].
target(OperationPerform);
}
@ -713,7 +713,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
static void stack_pei(AccessType, bool, const std::function<void(MicroOp)> &target) {
target(CycleFetchIncrementPC); // DO.
target(OperationConstructDirect);
target(OperationConstructDirectLong);
target(CycleFetchPreviousPCThrowaway); // IO.
target(CycleFetchIncrementData); // AAL.
@ -873,7 +873,7 @@ ProcessorStorage::ProcessorStorage() {
/* 0x28 PLP s */ op(stack_pull, PLP, AccessMode::Always8Bit);
/* 0x29 AND # */ op(immediate, AND);
/* 0x2a ROL A */ op(accumulator, ROL);
/* 0x2b PLD s */ op(stack_pld, PLD);
/* 0x2b PLD s */ op(stack_pld_plb, PLD, AccessMode::Always16Bit);
/* 0x2c BIT a */ op(absolute, BIT);
/* 0x2d AND a */ op(absolute, AND);
/* 0x2e ROL a */ op(absolute_rmw, ROL);
@ -1009,7 +1009,7 @@ ProcessorStorage::ProcessorStorage() {
/* 0xa8 TAY i */ op(implied, TAY);
/* 0xa9 LDA # */ op(immediate, LDA);
/* 0xaa TAX i */ op(implied, TAX);
/* 0xab PLB s */ op(stack_pull, PLB, AccessMode::Always8Bit);
/* 0xab PLB s */ op(stack_pld_plb, PLB, AccessMode::Always8Bit);
/* 0xac LDY a */ op(absolute, LDY);
/* 0xad LDA a */ op(absolute, LDA);
/* 0xae LDX a */ op(absolute, LDX);