diff --git a/Machines/Amiga/Amiga.cpp b/Machines/Amiga/Amiga.cpp index c53452704..a8b1aeb09 100644 --- a/Machines/Amiga/Amiga.cpp +++ b/Machines/Amiga/Amiga.cpp @@ -127,7 +127,7 @@ class ConcreteMachine: if(!(address & 0x2000)) chipset_.cia_b.write(reg, cycle.value8_high()); } - LOG("CIA " << (((address >> 12) & 3)^3) << " " << (cycle.operation & Microcycle::Read ? "read " : "write ") << std::dec << (reg & 0xf) << " of " << PADHEX(2) << +cycle.value8_low()); +// LOG("CIA " << (((address >> 12) & 3)^3) << " " << (cycle.operation & Microcycle::Read ? "read " : "write ") << std::dec << (reg & 0xf) << " of " << PADHEX(2) << +cycle.value8_low()); } else if(address >= 0xdf'f000 && address <= 0xdf'f1be) { chipset_.perform(cycle); } else { diff --git a/Machines/Amiga/Chipset.cpp b/Machines/Amiga/Chipset.cpp index 480890c35..89bb07f07 100644 --- a/Machines/Amiga/Chipset.cpp +++ b/Machines/Amiga/Chipset.cpp @@ -563,7 +563,7 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) { case Write(0x09a): ApplySetClear(interrupt_enable_); update_interrupts(); - LOG("Interrupt enable mask modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_enable_}); +// LOG("Interrupt enable mask modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_enable_}); break; case Read(0x01c): cycle.set_value16(interrupt_enable_); @@ -757,7 +757,7 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) { case Write(0x1a8): case Write(0x1aa): case Write(0x1ac): case Write(0x1ae): case Write(0x1b0): case Write(0x1b2): case Write(0x1b4): case Write(0x1b6): case Write(0x1b8): case Write(0x1ba): case Write(0x1bc): case Write(0x1be): { - LOG("Colour palette; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address); +// LOG("Colour palette; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address); // Store once in regular, linear order. const auto entry_address = (register_address - 0x180) >> 1;