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Use common macros for the two forms of Perform.

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Thomas Harte 2022-05-22 07:08:14 -04:00
parent 4993801741
commit 11a9a5c126
1 changed files with 29 additions and 51 deletions
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80
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -1233,6 +1233,18 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Access(operand_[next_operand_].high); // nW Access(operand_[next_operand_].high); // nW
MoveToNextOperand(StoreOperand_l); MoveToNextOperand(StoreOperand_l);
#define PerformDynamic() \
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( \
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
#define PerformSpecific(x) \
InstructionSet::M68k::perform< \
InstructionSet::M68k::Model::M68000, \
ProcessorBase, \
InstructionSet::M68k::Operation::x \
>( \
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
// //
// Various generic forms of perform. // Various generic forms of perform.
// //
@ -1241,21 +1253,18 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
if(operand_flags_ & 0x0c) MoveToState(StoreOperand) else MoveToState(Decode) if(operand_flags_ & 0x0c) MoveToState(StoreOperand) else MoveToState(Decode)
BeginState(Perform_np): BeginState(Perform_np):
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( PerformDynamic();
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
Prefetch(); // np Prefetch(); // np
MoveToWritePhase(); MoveToWritePhase();
BeginState(Perform_np_n): BeginState(Perform_np_n):
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( PerformDynamic();
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
Prefetch(); // np Prefetch(); // np
IdleBus(1); // n IdleBus(1); // n
MoveToWritePhase(); MoveToWritePhase();
BeginState(Perform_np_nn): BeginState(Perform_np_nn):
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( PerformDynamic();
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
Prefetch(); // np Prefetch(); // np
IdleBus(2); // nn IdleBus(2); // nn
MoveToWritePhase(); MoveToWritePhase();
@ -1308,8 +1317,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Prefetch(); // np Prefetch(); // np
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( PerformDynamic();
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
SetupDataAccess(0, select_flag_); SetupDataAccess(0, select_flag_);
Access(operand_[1].low); // nw Access(operand_[1].low); // nw
@ -1334,8 +1342,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
registers_[8 + instruction_.reg(1)].l -= 2; registers_[8 + instruction_.reg(1)].l -= 2;
Access(operand_[1].high); // nR Access(operand_[1].high); // nR
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( PerformDynamic();
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
SetupDataAccess(0, Microcycle::SelectWord); SetupDataAccess(0, Microcycle::SelectWord);
@ -1353,12 +1360,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
BeginState(CHK): BeginState(CHK):
Prefetch(); // np Prefetch(); // np
InstructionSet::M68k::perform< PerformSpecific(CHK);
InstructionSet::M68k::Model::M68000,
ProcessorBase,
InstructionSet::M68k::Operation::CHK
>(
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
// Proper next state will have been set by the flow controller // Proper next state will have been set by the flow controller
// call-in; just allow dispatch to whatever it was. // call-in; just allow dispatch to whatever it was.
@ -1385,12 +1387,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
BeginState(Scc_Dn): BeginState(Scc_Dn):
Prefetch(); // np Prefetch(); // np
InstructionSet::M68k::perform< PerformSpecific(Scc);
InstructionSet::M68k::Model::M68000,
ProcessorBase,
InstructionSet::M68k::Operation::Scc
>(
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
// Next state will be set by did_scc. // Next state will be set by did_scc.
break; break;
@ -1408,15 +1405,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(DBcc): BeginState(DBcc):
operand_[0] = registers_[instruction_.reg(0)]; operand_[0] = registers_[instruction_.reg(0)];
operand_[1].w = uint32_t(int16_t(prefetch_.w)); operand_[1].w = uint32_t(int16_t(prefetch_.w));
PerformSpecific(DBcc);
InstructionSet::M68k::perform<
InstructionSet::M68k::Model::M68000,
ProcessorBase,
InstructionSet::M68k::Operation::DBcc
>(
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
// Just do the write-back here.
registers_[instruction_.reg(0)].w = operand_[0].w; registers_[instruction_.reg(0)].w = operand_[0].w;
// Next state was set by complete_dbcc. // Next state was set by complete_dbcc.
@ -1452,18 +1441,14 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
BeginState(Bcc_b): BeginState(Bcc_b):
operand_[0].b = uint8_t(opcode_); operand_[0].b = uint8_t(opcode_);
PerformSpecific(Bccb);
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
// Next state was set by complete_bcc. // Next state was set by complete_bcc.
break; break;
BeginState(Bcc_w): BeginState(Bcc_w):
operand_[0].w = prefetch_.w; operand_[0].w = prefetch_.w;
PerformSpecific(Bccw);
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
// Next state was set by complete_bcc. // Next state was set by complete_bcc.
break; break;
@ -1508,8 +1493,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
registers_[15].l -= 2; registers_[15].l -= 2;
// Get the new PC. // Get the new PC.
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( PerformDynamic();
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
Prefetch(); // np Prefetch(); // np
Prefetch(); // np Prefetch(); // np
@ -1540,8 +1524,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// BSET, BCHG, BCLR // BSET, BCHG, BCLR
// //
BeginState(BCHG_BSET_Dn): BeginState(BCHG_BSET_Dn):
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( PerformDynamic();
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
Prefetch(); Prefetch();
IdleBus(1 + dynamic_instruction_length_); IdleBus(1 + dynamic_instruction_length_);
@ -1549,12 +1532,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
MoveToState(Decode); MoveToState(Decode);
BeginState(BCLR_Dn): BeginState(BCLR_Dn):
InstructionSet::M68k::perform< PerformSpecific(BCLR);
InstructionSet::M68k::Model::M68000,
ProcessorBase,
InstructionSet::M68k::Operation::BCLR
>(
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
Prefetch(); Prefetch();
IdleBus(2 + dynamic_instruction_length_); IdleBus(2 + dynamic_instruction_length_);
@ -1653,8 +1631,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// //
BeginState(LogicalToSR): BeginState(LogicalToSR):
// Perform the operation. // Perform the operation.
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( PerformDynamic();
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
// Recede the program counter and prefetch twice. // Recede the program counter and prefetch twice.
program_counter_.l -= 2; program_counter_.l -= 2;
@ -1860,8 +1837,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
exception_vector_ = -1; exception_vector_ = -1;
// Perform the instruction. // Perform the instruction.
InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>( PerformDynamic();
instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
// Delay the correct amount of time. // Delay the correct amount of time.
IdleBus(dynamic_instruction_length_); IdleBus(dynamic_instruction_length_);
@ -1893,6 +1869,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
assert(false); assert(false);
}} }}
#undef PerformDynamic
#undef PerformSpecific
#undef Prefetch #undef Prefetch
#undef ReadProgramWord #undef ReadProgramWord
#undef ReadDataWord #undef ReadDataWord