From 125d97cc41e87a0a71c3322f41be1641855e6b2f Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 3 Apr 2022 08:55:28 -0400
Subject: [PATCH] Complete floating point tests.

---
 InstructionSets/PowerPC/Instruction.hpp       | 35 ++++++++++++++++---
 .../DingusdevPowerPCTests.mm                  | 12 +++++++
 2 files changed, 43 insertions(+), 4 deletions(-)

diff --git a/InstructionSets/PowerPC/Instruction.hpp b/InstructionSets/PowerPC/Instruction.hpp
index 5e654450d..ddd0dc410 100644
--- a/InstructionSets/PowerPC/Instruction.hpp
+++ b/InstructionSets/PowerPC/Instruction.hpp
@@ -614,17 +614,44 @@ enum class Operation: uint8_t {
 	/// crfD(), crfS()
 	mcrfs,
 
-
+	/// Move to condition register from XER.
+	/// mcrxr
+	/// crfD()
 	mcrxr,
-	mfcr, mffsx, mfmsr, mfspr, mfsr, mfsrin,
+
+	/// Move from condition register.
+	/// mfcr
+	/// rD()
+	mfcr,
+
+	mffsx, mfmsr, mfspr, mfsr, mfsrin,
 
 	/// Move to condition register fields.
 	/// mtcrf
 	/// rS(), crm()
 	mtcrf,
 
-	mtfsb0x, mtfsb1x, mtfsfx,
-	mtfsfix, mtmsr, mtspr, mtsr, mtsrin,
+	/// Move to FPSCR bit 0.
+	/// mtfsb0 mtfsb0.
+	/// crbD()
+	mtfsb0x,
+
+	/// Move to FPSCR bit 1.
+	/// mtfsb1 mtfsb1.
+	/// crbD()
+	mtfsb1x,
+
+	/// Move to FPSCR fields.
+	/// mtfsf mtfsf.
+	/// fm(), frB()	[rc()]
+	mtfsfx,
+
+	/// Move to FPSCR field immediate.
+	/// mtfsfi mtfsfi.
+	/// crfD(), imm()
+	mtfsfix,
+
+	mtmsr, mtspr, mtsr, mtsrin,
 
 	/// Multiply high word.
 	/// mulhw mulgw.
diff --git a/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm b/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm
index fc9842ba3..f0e03e9ea 100644
--- a/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm	
@@ -298,6 +298,18 @@ NSString *offset(Instruction instruction) {
 				XCTAssertEqual([columns[5] hexInt], instruction.simm());
 			break;
 
+			case Operation::mtfsfx:
+				AssertEqualOperationNameE(operation, @"mtfsfx", instruction);
+				XCTAssertEqual([columns[3] intValue], instruction.fm());
+				AssertEqualFR(columns[4], instruction.frB());
+			break;
+
+			case Operation::mtfsfix:
+				AssertEqualOperationNameE(operation, @"mtfsfix", instruction);
+				XCTAssertEqualObjects(columns[3], conditionreg(instruction.crfD()));
+				XCTAssertEqual([columns[4] intValue], instruction.imm());
+			break;
+
 #define NoArg(x)	\
 			case Operation::x:	\
 				AssertEqualOperationName(operation, @#x);	\