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Starts adjusting the concept of a Source.
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Thomas Harte
parent
cd5ca3f65b
commit
12df7112da
@ -102,8 +102,8 @@ std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *
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case start + 0x01: MemRegReg(operation, MemReg_Reg, 2); break; \
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case start + 0x02: MemRegReg(operation, Reg_MemReg, 1); break; \
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case start + 0x03: MemRegReg(operation, Reg_MemReg, 2); break; \
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case start + 0x04: RegData(operation, AL, 1); break; \
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case start + 0x05: RegData(operation, AX, 2)
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case start + 0x04: RegData(operation, eAX, 1); break; \
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case start + 0x05: RegData(operation, eAX, 2)
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PartialBlock(0x00, ADD); break;
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case 0x06: Complete(PUSH, ES, None, 2); break;
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@ -137,23 +137,23 @@ std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *
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PartialBlock(0x30, XOR); break;
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case 0x36: segment_override_ = Source::SS; break;
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case 0x37: Complete(AAA, AL, AX, 1); break;
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case 0x37: Complete(AAA, AL, eAX, 2); break;
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PartialBlock(0x38, CMP); break;
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case 0x3e: segment_override_ = Source::DS; break;
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case 0x3f: Complete(AAS, AL, AX, 1); break;
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case 0x3f: Complete(AAS, AL, eAX, 2); break;
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#undef PartialBlock
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#define RegisterBlock(start, operation) \
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case start + 0x00: Complete(operation, AX, AX, 2); break; \
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case start + 0x01: Complete(operation, CX, CX, 2); break; \
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case start + 0x02: Complete(operation, DX, DX, 2); break; \
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case start + 0x03: Complete(operation, BX, BX, 2); break; \
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case start + 0x04: Complete(operation, SP, SP, 2); break; \
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case start + 0x05: Complete(operation, BP, BP, 2); break; \
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case start + 0x06: Complete(operation, SI, SI, 2); break; \
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case start + 0x07: Complete(operation, DI, DI, 2)
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#define RegisterBlock(start, operation) \
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case start + 0x00: Complete(operation, eAX, eAX, 2); break; \
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case start + 0x01: Complete(operation, eCX, eCX, 2); break; \
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case start + 0x02: Complete(operation, eDX, eDX, 2); break; \
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case start + 0x03: Complete(operation, eBX, eBX, 2); break; \
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case start + 0x04: Complete(operation, eSP, eSP, 2); break; \
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case start + 0x05: Complete(operation, eBP, eBP, 2); break; \
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case start + 0x06: Complete(operation, eSI, eSI, 2); break; \
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case start + 0x07: Complete(operation, eDI, eDI, 2)
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RegisterBlock(0x40, INC); break;
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RegisterBlock(0x48, DEC); break;
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@ -231,16 +231,16 @@ std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *
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case 0x8f: MemRegReg(POP, MemRegPOP, 2); break;
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case 0x90: Complete(NOP, None, None, 0); break; // Or XCHG AX, AX?
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case 0x91: Complete(XCHG, AX, CX, 2); break;
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case 0x92: Complete(XCHG, AX, DX, 2); break;
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case 0x93: Complete(XCHG, AX, BX, 2); break;
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case 0x94: Complete(XCHG, AX, SP, 2); break;
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case 0x95: Complete(XCHG, AX, BP, 2); break;
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case 0x96: Complete(XCHG, AX, SI, 2); break;
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case 0x97: Complete(XCHG, AX, DI, 2); break;
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case 0x91: Complete(XCHG, eAX, eCX, 2); break;
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case 0x92: Complete(XCHG, eAX, eDX, 2); break;
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case 0x93: Complete(XCHG, eAX, eBX, 2); break;
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case 0x94: Complete(XCHG, eAX, eSP, 2); break;
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case 0x95: Complete(XCHG, eAX, eBP, 2); break;
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case 0x96: Complete(XCHG, eAX, eSI, 2); break;
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case 0x97: Complete(XCHG, eAX, eDI, 2); break;
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case 0x98: Complete(CBW, AL, AH, 1); break;
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case 0x99: Complete(CWD, AX, DX, 2); break;
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case 0x99: Complete(CWD, eAX, eDX, 2); break;
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case 0x9a: Far(CALLF); break;
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case 0x9b: Complete(WAIT, None, None, 0); break;
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case 0x9c: Complete(PUSHF, None, None, 2); break;
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@ -249,16 +249,16 @@ std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *
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case 0x9f: Complete(LAHF, None, None, 1); break;
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case 0xa0: RegAddr(MOV, AL, 1, 1); break;
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case 0xa1: RegAddr(MOV, AX, 2, 2); break;
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case 0xa1: RegAddr(MOV, eAX, 2, 2); break;
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case 0xa2: AddrReg(MOV, AL, 1, 1); break;
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case 0xa3: AddrReg(MOV, AX, 2, 2); break;
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case 0xa3: AddrReg(MOV, eAX, 2, 2); break;
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case 0xa4: Complete(MOVS, None, None, 1); break;
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case 0xa5: Complete(MOVS, None, None, 2); break;
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case 0xa6: Complete(CMPS, None, None, 1); break;
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case 0xa7: Complete(CMPS, None, None, 2); break;
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case 0xa8: RegData(TEST, AL, 1); break;
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case 0xa9: RegData(TEST, AX, 2); break;
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case 0xa9: RegData(TEST, eAX, 2); break;
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case 0xaa: Complete(STOS, None, None, 1); break;
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case 0xab: Complete(STOS, None, None, 2); break;
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case 0xac: Complete(LODS, None, None, 1); break;
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@ -266,22 +266,22 @@ std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *
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case 0xae: Complete(SCAS, None, None, 1); break;
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case 0xaf: Complete(SCAS, None, None, 2); break;
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case 0xb0: RegData(MOV, AL, 1); break;
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case 0xb1: RegData(MOV, CL, 1); break;
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case 0xb2: RegData(MOV, DL, 1); break;
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case 0xb3: RegData(MOV, BL, 1); break;
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case 0xb4: RegData(MOV, AH, 1); break;
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case 0xb5: RegData(MOV, CH, 1); break;
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case 0xb6: RegData(MOV, DH, 1); break;
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case 0xb7: RegData(MOV, BH, 1); break;
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case 0xb8: RegData(MOV, AX, 2); break;
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case 0xb9: RegData(MOV, CX, 2); break;
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case 0xba: RegData(MOV, DX, 2); break;
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case 0xbb: RegData(MOV, BX, 2); break;
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case 0xbc: RegData(MOV, SP, 2); break;
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case 0xbd: RegData(MOV, BP, 2); break;
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case 0xbe: RegData(MOV, SI, 2); break;
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case 0xbf: RegData(MOV, DI, 2); break;
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case 0xb0: RegData(MOV, eAX, 1); break;
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case 0xb1: RegData(MOV, eCX, 1); break;
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case 0xb2: RegData(MOV, eDX, 1); break;
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case 0xb3: RegData(MOV, eBX, 1); break;
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case 0xb4: RegData(MOV, AH, 1); break;
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case 0xb5: RegData(MOV, CH, 1); break;
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case 0xb6: RegData(MOV, DH, 1); break;
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case 0xb7: RegData(MOV, BH, 1); break;
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case 0xb8: RegData(MOV, eAX, 2); break;
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case 0xb9: RegData(MOV, eCX, 2); break;
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case 0xba: RegData(MOV, eDX, 2); break;
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case 0xbb: RegData(MOV, eBX, 2); break;
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case 0xbc: RegData(MOV, eSP, 2); break;
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case 0xbd: RegData(MOV, eBP, 2); break;
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case 0xbe: RegData(MOV, eSI, 2); break;
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case 0xbf: RegData(MOV, eDI, 2); break;
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case 0xc2: RegData(RETN, None, 2); break;
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case 0xc3: Complete(RETN, None, None, 2); break;
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@ -320,8 +320,8 @@ std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *
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operation_size_ = 1 + (instr_ & 1);
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source_ = Source::CL;
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break;
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case 0xd4: RegData(AAM, AX, 1); break;
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case 0xd5: RegData(AAD, AX, 1); break;
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case 0xd4: RegData(AAM, eAX, 1); break;
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case 0xd5: RegData(AAD, eAX, 1); break;
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case 0xd7: Complete(XLAT, None, None, 1); break;
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@ -354,6 +354,10 @@ std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *
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case 0xee: Complete(OUT, AL, DX, 1); break;
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case 0xef: Complete(OUT, AX, DX, 2); break;
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case 0xf0: lock_ = true; break;
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case 0xf2: repetition_ = Repetition::RepNE; break;
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case 0xf3: repetition_ = Repetition::RepE; break;
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case 0xf4: Complete(HLT, None, None, 1); break;
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case 0xf5: Complete(CMC, None, None, 1); break;
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case 0xf6: MemRegReg(Invalid, MemRegTEST_to_IDIV, 1); break;
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@ -368,11 +372,6 @@ std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *
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case 0xfe: MemRegReg(Invalid, MemRegINC_DEC, 1); break;
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case 0xff: MemRegReg(Invalid, MemRegINC_to_PUSH, 1); break;
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// Other prefix bytes.
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case 0xf0: lock_ = true; break;
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case 0xf2: repetition_ = Repetition::RepNE; break;
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case 0xf3: repetition_ = Repetition::RepE; break;
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}
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}
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@ -422,11 +421,11 @@ std::pair<int, InstructionSet::x86::Instruction> Decoder::decode(const uint8_t *
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constexpr Source reg_table[3][8] = {
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{},
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{
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Source::AL, Source::CL, Source::DL, Source::BL,
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Source::AH, Source::CH, Source::DH, Source::BH,
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Source::AL, Source::eCX, Source::eDX, Source::eBX,
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Source::AH, Source::CH, Source::DH, Source::BH,
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}, {
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Source::AX, Source::CX, Source::DX, Source::BX,
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Source::SP, Source::BP, Source::SI, Source::DI,
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Source::eAX, Source::eCX, Source::eDX, Source::eBX,
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Source::eSP, Source::eBP, Source::eSI, Source::eDI,
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}
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};
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switch(mod) {
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@ -318,34 +318,82 @@ enum class Size: uint8_t {
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};
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enum class Source: uint8_t {
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None,
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CS, DS, ES, SS,
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// These are in SIB order; this matters for packing later on.
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// Whether each refers to e.g. EAX or AX depends on the
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// instruction's data size.
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eAX, eCX, eDX, eBX, eSP, eBP, eSI, eDI,
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AL, AH, AX,
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BL, BH, BX,
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CL, CH, CX,
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DL, DH, DX,
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// Selectors are provided as a group.
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CS, DS, ES, SS, FS, GS,
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SI, DI,
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BP, SP,
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DirectAddress,
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Immediate,
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Indirect,
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// Legacy 8-bit registers that can't be described as e.g. 8-bit eAX,
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// or where the source is 8-bit but the destination is 16-bit.
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AL, BL, CL, DL,
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AH, BH, CH, DH,
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// TODO: can these all be eliminated in favour of eAX,2, etc?
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AX, BX, CX, DX,
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// TODO: compact and replace with a reference to a SIB.
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IndBXPlusSI,
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IndBXPlusDI,
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IndBPPlusSI,
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IndBPPlusDI,
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IndSI,
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IndDI,
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DirectAddress,
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IndBP,
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IndBX,
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Immediate
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/// @c None can be treated as a source that produces 0 when encountered;
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/// it is semantically valid to receive it with that meaning in some contexts —
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/// e.g. to indicate no index in indirect addressing.
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None,
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};
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enum class Repetition: uint8_t {
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None, RepE, RepNE
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};
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/// Provides a 32-bit-style scale, index and base; to produce the address this represents,
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/// calcluate base() + (index() << scale()).
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///
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/// This form of indirect addressing is used to describe both 16- and 32-bit indirect addresses,
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/// even though it is a superset of that supported prior to the 80386.
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class ScaleIndexBase {
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public:
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ScaleIndexBase(uint8_t sib) : sib_(sib) {}
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ScaleIndexBase(int scale, Source index, Source base) : sib_(uint8_t(scale << 6 | (int(index != Source::None ? index : Source::eSI) << 3) | int(base))) {}
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/// @returns the power of two by which to multiply @c index() before adding it to @c base().
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int scale() const {
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return sib_ >> 6;
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}
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/// @returns the @c index for this address; this is guaranteed to be one of eAX, eBX, eCX, eDX, None, eBP, eSI or eDI.
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Source index() const {
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constexpr Source sources[] = {
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Source::eAX, Source::eCX, Source::eDX, Source::eBX, Source::None, Source::eBP, Source::eSI, Source::eDI,
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};
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static_assert(sizeof(sources) == 8);
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return sources[(sib_ >> 3) & 0x7];
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}
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/// @returns the @c base for this address; this is guaranteed to be one of eAX, eBX, eCX, eDX, eSP, eBP, eSI or eDI.
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Source base() const {
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return Source(sib_ & 0x7);
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}
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private:
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// Data is stored directly as an 80386 SIB byte.
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const uint8_t sib_ = 0;
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};
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static_assert(sizeof(ScaleIndexBase) == 1);
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static_assert(alignof(ScaleIndexBase) == 1);
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class Instruction {
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public:
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Operation operation = Operation::Invalid;
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