6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-02-16 18:30:32 +00:00
Code Issues Projects Releases Wiki Activity

I think 3 is what I'm aiming for here.

Browse Source 
But this probably isn't correct for IO cycles.
This commit is contained in:
Thomas Harte 2021-04-02 07:36:57 -04:00
parent 044ac949ba
commit 14663bd06b
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Machines/Sinclair/ZXSpectrum/ZXSpectrum.cpp
View File

@ -206,8 +206,8 @@ template<Model model> class ConcreteMachine:
// the read/write, then complete the bus cycle. Only via the 48/128k Spectrum contended
// timings am I now learning what happens with MREQ during extended read/write bus cycles
// (i.e. those longer than 3 cycles)
if(cycle.length > HalfCycles(5)) {
advance(HalfCycles(5));
if(cycle.length > HalfCycles(3)) {
advance(HalfCycles(3));
} else {
advance(cycle.length);
}
@ -368,8 +368,8 @@ template<Model model> class ConcreteMachine:
break;
}
if(cycle.length > HalfCycles(5)) {
advance(cycle.length - HalfCycles(5));
if(cycle.length > HalfCycles(3)) {
advance(cycle.length - HalfCycles(3));
}
return HalfCycles(0);
}