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Add enough to make AND masks the default case.
This commit is contained in:
Thomas Harte
parent
6ca30a16ca
commit
1538500903
@ -176,6 +176,11 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
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static constexpr auto AlterableAddressingModes = Dn | An | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl;
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static constexpr auto AlterableAddressingModesNoAn = AlterableAddressingModes & ~An;
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//
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// Control [flow] addressing modes.
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//
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static constexpr auto ControlAddressingModes = Ind | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn;
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switch(op) {
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default: return NoOperandMask::value;
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@ -234,23 +239,45 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
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AlterableAddressingModes
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>::value;
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case OpT(Operation::ANDItoCCR):
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case OpT(Operation::ANDItoCCR): case OpT(Operation::ANDItoSR):
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case OpT(Operation::Bccw): case OpT(Operation::Bccl):
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case OpT(Operation::BSRl): case OpT(Operation::BSRw):
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case OpT(Operation::EORItoCCR):
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case OpT(Operation::EORItoCCR): case OpT(Operation::EORItoSR):
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case OpT(Operation::ORItoCCR): case OpT(Operation::ORItoSR):
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case OpT(Operation::STOP):
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return ~OneOperandMask<
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Imm
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>::value;
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case OpT(Operation::ASLb): case OpT(Operation::ASLw): case OpT(Operation::ASLl):
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case OpT(Operation::ASRb): case OpT(Operation::ASRw): case OpT(Operation::ASRl):
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case OpT(Operation::LSLb): case OpT(Operation::LSLw): case OpT(Operation::LSLl):
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case OpT(Operation::LSRb): case OpT(Operation::LSRw): case OpT(Operation::LSRl):
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case OpT(Operation::ROLb): case OpT(Operation::ROLw): case OpT(Operation::ROLl):
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case OpT(Operation::RORb): case OpT(Operation::RORw): case OpT(Operation::RORl):
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case OpT(Operation::ROXLb): case OpT(Operation::ROXLw): case OpT(Operation::ROXLl):
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case OpT(Operation::ROXRb): case OpT(Operation::ROXRw): case OpT(Operation::ROXRl):
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return ~TwoOperandMask<
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Quick | Dn,
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Dn
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>::value;
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case OpT(Operation::ASLm):
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case OpT(Operation::ASRm):
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case OpT(Operation::LSLm):
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case OpT(Operation::LSRm):
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case OpT(Operation::ROLm):
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case OpT(Operation::RORm):
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case OpT(Operation::ROXLm):
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case OpT(Operation::ROXRm):
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return ~OneOperandMask<
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Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl
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>::value;
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case OpT(Operation::Bccb):
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case OpT(Operation::BSRb):
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case OpT(Operation::TRAP):
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return ~OneOperandMask<
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Quick
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>::value;
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@ -340,6 +367,7 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
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>::value;
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case OpT(Operation::EXTbtow): case OpT(Operation::EXTwtol):
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case OpT(Operation::SWAP):
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return ~OneOperandMask<
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Dn
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>::value;
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@ -347,14 +375,38 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
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case OpT(Operation::JMP):
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case OpT(Operation::JSR):
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return ~OneOperandMask<
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Ind | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn
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ControlAddressingModes
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>::value;
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case OpT(Operation::LEA):
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return ~TwoOperandMask<
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ControlAddressingModes,
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An
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>::value;
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case OpT(Operation::LINKw):
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return ~TwoOperandMask<
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An,
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Imm
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>::value;
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case OpT(Operation::NOP):
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case OpT(Operation::RTE):
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case OpT(Operation::RTS):
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case OpT(Operation::TRAPV):
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case OpT(Operation::RTR):
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return ~NoOperandMask::value;
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case OpT(Operation::UNLINK):
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case OpT(Operation::MOVEtoUSP):
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case OpT(Operation::MOVEfromUSP):
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return ~OneOperandMask<
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An
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>::value;
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}
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}
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/// Provides a post-decoding validation step — primarily ensures that the prima facie addressing modes are supported by the operation.
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// TODO: once complete and working, see how ugly it would be to incorpoate these tests into the main
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// decoding switches.
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template <Model model>
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template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated(Preinstruction original) {
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if constexpr (!validate) {
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@ -362,44 +414,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
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}
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switch(op) {
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default: return original;
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// All operations converted to the AND test.
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case OpT(Operation::ABCD):
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case OpT(Operation::ADDXb): case OpT(Operation::ADDXw): case OpT(Operation::ADDXl):
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case ADDtoRb: case ADDtoRw: case ADDtoRl:
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case ADDIb: case ADDIl: case ADDIw:
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case ADDtoMb: case ADDtoMw: case ADDtoMl:
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case OpT(Operation::ADDAw): case OpT(Operation::ADDAl):
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case ADDQb: case ADDQw: case ADDQl:
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case ANDtoRb: case ANDtoRw: case ANDtoRl:
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case ANDtoMb: case ANDtoMw: case ANDtoMl:
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case ANDIb: case ANDIl: case ANDIw:
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case OpT(Operation::ANDItoCCR):
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case OpT(Operation::ASLb): case OpT(Operation::ASLw): case OpT(Operation::ASLl):
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case OpT(Operation::ASRb): case OpT(Operation::ASRw): case OpT(Operation::ASRl):
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case OpT(Operation::Bccb): case OpT(Operation::Bccw): case OpT(Operation::Bccl):
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case OpT(Operation::BCHG): case BCHGI:
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case OpT(Operation::BCLR): case BCLRI:
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case OpT(Operation::BSET): case BSETI:
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case OpT(Operation::BSRb): case OpT(Operation::BSRw): case OpT(Operation::BSRl):
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case OpT(Operation::BTST): case BTSTI:
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case OpT(Operation::CHK):
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case OpT(Operation::CLRb): case OpT(Operation::CLRw): case OpT(Operation::CLRl):
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case OpT(Operation::CMPb): case OpT(Operation::CMPw): case OpT(Operation::CMPl):
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case OpT(Operation::CMPAw): case OpT(Operation::CMPAl):
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case CMPIb: case CMPIl: case CMPIw:
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case CMPMb: case CMPMw: case CMPMl:
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case OpT(Operation::DBcc):
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case OpT(Operation::DIVS): case OpT(Operation::DIVU):
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case OpT(Operation::EORb): case OpT(Operation::EORw): case OpT(Operation::EORl):
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case EORIb: case EORIw: case EORIl:
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case OpT(Operation::EORItoCCR):
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case EXGRtoR: case EXGAtoA: case EXGRtoA:
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case OpT(Operation::EXTbtow): case OpT(Operation::EXTwtol):
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case OpT(Operation::JMP):
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case OpT(Operation::JSR):
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case OpT(Operation::NBCD): {
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default: {
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const auto invalid = invalid_operands<op>();
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const auto observed = operand_mask(original);
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return (observed & invalid) ? Preinstruction() : original;
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@ -579,7 +594,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
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}
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// LEA, PEA
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case OpT(Operation::LEA): case OpT(Operation::PEA):
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case OpT(Operation::PEA):
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switch(original.mode<0>()) {
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default: return original;
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@ -632,22 +647,6 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
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return Preinstruction();
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}
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case OpT(Operation::ASLm): case OpT(Operation::ASRm):
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case OpT(Operation::LSLm): case OpT(Operation::LSRm):
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case OpT(Operation::ROLm): case OpT(Operation::RORm):
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case OpT(Operation::ROXLm): case OpT(Operation::ROXRm):
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switch(original.mode<0>()) {
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default: return original;
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case AddressingMode::DataRegisterDirect:
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case AddressingMode::AddressRegisterDirect:
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case AddressingMode::ImmediateData:
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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case AddressingMode::None:
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return Preinstruction();
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}
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case MOVEMtoMw: case MOVEMtoMl:
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switch(original.mode<1>()) {
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default: return original;
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