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Merge branch 'master' into AppleIIgs
This commit is contained in:
Thomas Harte
commit
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347
InstructionSets/PowerPC/Decoder.cpp
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347
InstructionSets/PowerPC/Decoder.cpp
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@ -0,0 +1,347 @@
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//
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// Decoder.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 12/30/20.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#include "Decoder.hpp"
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using namespace CPU::Decoder::PowerPC;
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Decoder::Decoder(Model model) : model_(model) {}
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Instruction Decoder::decode(uint32_t opcode) {
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// Quick bluffer's guide to PowerPC instruction encoding:
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//
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// There is a six-bit field at the very top of the instruction.
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// Sometimes that fully identifies an instruction, but usually
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// it doesn't.
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//
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// There is an addition 9- or 10-bit field starting one bit above
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// least significant that disambiguates the rest. Strictly speaking
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// it's a 10-bit field, but the mnemonics for many instructions treat
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// it as a 9-bit field with a flag at the top.
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//
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// I've decided to hew directly to the mnemonics.
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//
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// Various opcodes in the 1995 documentation define reserved bits,
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// which are given the nominal value of 0. It does not give a formal
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// definition of a reserved bit. As a result this code does not
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// currently check the value of reserved bits. That may need to change
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// if/when I add support for extended instruction sets.
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#define Bind(mask, operation) case mask: return Instruction(Operation::operation, opcode);
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#define BindSupervisor(mask, operation) case mask: return Instruction(Operation::operation, opcode, true);
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#define BindConditional(condition, mask, operation) \
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case mask: \
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if(condition()) return Instruction(Operation::operation, opcode); \
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return Instruction(opcode);
|
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#define BindSupervisorConditional(condition, mask, operation) \
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case mask: \
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if(condition()) return Instruction(Operation::operation, opcode, true); \
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return Instruction(opcode);
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#define Six(x) (unsigned(x) << 26)
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#define SixTen(x, y) (Six(x) | ((y) << 1))
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// First pass: weed out all those instructions identified entirely by the
|
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// top six bits.
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switch(opcode & Six(0b111111)) {
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default: break;
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BindConditional(is64bit, Six(0b000010), tdi);
|
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|
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Bind(Six(0b000011), twi);
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Bind(Six(0b000111), mulli);
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Bind(Six(0b001000), subfic);
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Bind(Six(0b001100), addic); Bind(Six(0b001101), addic_);
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Bind(Six(0b001110), addi); Bind(Six(0b001111), addis);
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case Six(0b010000): {
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// This might be a bcx, but check for a valid bo field.
|
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switch((opcode >> 21) & 0x1f) {
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case 0: case 1: case 2: case 3: case 4: case 5:
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case 8: case 9: case 10: case 11: case 12: case 13:
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case 16: case 17: case 18: case 19: case 20:
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return Instruction(Operation::bcx, opcode);
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default: return Instruction(opcode);
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}
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} break;
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Bind(Six(0b010010), bx);
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Bind(Six(0b010100), rlwimix);
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Bind(Six(0b010101), rlwinmx);
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Bind(Six(0b010111), rlwnmx);
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|
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Bind(Six(0b011000), ori); Bind(Six(0b011001), oris);
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Bind(Six(0b011010), xori); Bind(Six(0b011011), xoris);
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Bind(Six(0b011100), andi_); Bind(Six(0b011101), andis_);
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Bind(Six(0b100000), lwz); Bind(Six(0b100001), lwzu);
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Bind(Six(0b100010), lbz); Bind(Six(0b100011), lbzu);
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Bind(Six(0b100100), stw); Bind(Six(0b100101), stwu);
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Bind(Six(0b100110), stb); Bind(Six(0b100111), stbu);
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Bind(Six(0b101000), lhz); Bind(Six(0b101001), lhzu);
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Bind(Six(0b101010), lha); Bind(Six(0b101011), lhau);
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Bind(Six(0b101100), sth); Bind(Six(0b101101), sthu);
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Bind(Six(0b101110), lmw); Bind(Six(0b101111), stmw);
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Bind(Six(0b110000), lfs); Bind(Six(0b110001), lfsu);
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Bind(Six(0b110010), lfd); Bind(Six(0b110011), lfdu);
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Bind(Six(0b110100), stfs); Bind(Six(0b110101), stfsu);
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Bind(Six(0b110110), stfd); Bind(Six(0b110111), stfdu);
|
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|
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BindConditional(is601, Six(9), dozi);
|
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BindConditional(is601, Six(22), rlmix);
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|
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Bind(Six(0b001010), cmpli); Bind(Six(0b001011), cmpi);
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}
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// Second pass: all those with a top six bits and a bottom nine or ten.
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switch(opcode & SixTen(0b111111, 0b1111111111)) {
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default: break;
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// 64-bit instructions.
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BindConditional(is64bit, SixTen(0b011111, 0b0000001001), mulhdux); BindConditional(is64bit, SixTen(0b011111, 0b1000001001), mulhdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0000010101), ldx);
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BindConditional(is64bit, SixTen(0b011111, 0b0000011011), sldx);
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BindConditional(is64bit, SixTen(0b011111, 0b0000110101), ldux);
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BindConditional(is64bit, SixTen(0b011111, 0b0000111010), cntlzdx);
|
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BindConditional(is64bit, SixTen(0b011111, 0b0001000100), td);
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BindConditional(is64bit, SixTen(0b011111, 0b0001001001), mulhdx); BindConditional(is64bit, SixTen(0b011111, 0b1001001001), mulhdx);
|
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BindConditional(is64bit, SixTen(0b011111, 0b0001010100), ldarx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010010101), stdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010110101), stdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0011101001), mulld); BindConditional(is64bit, SixTen(0b011111, 0b1011101001), mulld);
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BindConditional(is64bit, SixTen(0b011111, 0b0101010101), lwax);
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BindConditional(is64bit, SixTen(0b011111, 0b0101110101), lwaux);
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BindConditional(is64bit, SixTen(0b011111, 0b1100111011), sradix); BindConditional(is64bit, SixTen(0b011111, 0b1100111010), sradix);
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BindConditional(is64bit, SixTen(0b011111, 0b0110110010), slbie);
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BindConditional(is64bit, SixTen(0b011111, 0b0111001001), divdux); BindConditional(is64bit, SixTen(0b011111, 0b1111001001), divdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0111101001), divdx); BindConditional(is64bit, SixTen(0b011111, 0b1111101001), divdx);
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BindConditional(is64bit, SixTen(0b011111, 0b1000011011), srdx);
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BindConditional(is64bit, SixTen(0b011111, 0b1100011010), sradx);
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BindConditional(is64bit, SixTen(0b111111, 0b1111011010), extsw);
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// Power instructions; these are all taken from the MPC601 manual rather than
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// the PowerPC Programmer's Reference Guide, hence the decimal encoding of the
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// ten-bit field.
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BindConditional(is601, SixTen(0b011111, 360), absx); BindConditional(is601, SixTen(0b011111, 512 + 360), absx);
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BindConditional(is601, SixTen(0b011111, 531), clcs);
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BindConditional(is601, SixTen(0b011111, 331), divx); BindConditional(is601, SixTen(0b011111, 512 + 331), divx);
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BindConditional(is601, SixTen(0b011111, 363), divsx); BindConditional(is601, SixTen(0b011111, 512 + 363), divsx);
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BindConditional(is601, SixTen(0b011111, 264), dozx); BindConditional(is601, SixTen(0b011111, 512 + 264), dozx);
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BindConditional(is601, SixTen(0b011111, 277), lscbxx);
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BindConditional(is601, SixTen(0b011111, 29), maskgx);
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BindConditional(is601, SixTen(0b011111, 541), maskirx);
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BindConditional(is601, SixTen(0b011111, 107), mulx); BindConditional(is601, SixTen(0b011111, 512 + 107), mulx);
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BindConditional(is601, SixTen(0b011111, 488), nabsx); BindConditional(is601, SixTen(0b011111, 512 + 488), nabsx);
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BindConditional(is601, SixTen(0b011111, 537), rribx);
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BindConditional(is601, SixTen(0b011111, 153), slex);
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BindConditional(is601, SixTen(0b011111, 217), sleqx);
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BindConditional(is601, SixTen(0b011111, 184), sliqx);
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BindConditional(is601, SixTen(0b011111, 248), slliqx);
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BindConditional(is601, SixTen(0b011111, 216), sllqx);
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BindConditional(is601, SixTen(0b011111, 152), slqx);
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BindConditional(is601, SixTen(0b011111, 952), sraiqx);
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BindConditional(is601, SixTen(0b011111, 920), sraqx);
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BindConditional(is601, SixTen(0b011111, 665), srex);
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BindConditional(is601, SixTen(0b011111, 921), sreax);
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BindConditional(is601, SixTen(0b011111, 729), sreqx);
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BindConditional(is601, SixTen(0b011111, 696), sriqx);
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BindConditional(is601, SixTen(0b011111, 760), srliqx);
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BindConditional(is601, SixTen(0b011111, 728), srlqx);
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BindConditional(is601, SixTen(0b011111, 664), srqx);
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// 32-bit instructions.
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Bind(SixTen(0b010011, 0b0000000000), mcrf);
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Bind(SixTen(0b010011, 0b0000010000), bclrx);
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Bind(SixTen(0b010011, 0b0000100001), crnor);
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Bind(SixTen(0b010011, 0b0000110010), rfi);
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Bind(SixTen(0b010011, 0b0010000001), crandc);
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Bind(SixTen(0b010011, 0b0010010110), isync);
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Bind(SixTen(0b010011, 0b0011000001), crxor);
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Bind(SixTen(0b010011, 0b0011100001), crnand);
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Bind(SixTen(0b010011, 0b0100000001), crand);
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Bind(SixTen(0b010011, 0b0100100001), creqv);
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Bind(SixTen(0b010011, 0b0110100001), crorc);
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Bind(SixTen(0b010011, 0b0111000001), cror);
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Bind(SixTen(0b010011, 0b1000010000), bcctrx);
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Bind(SixTen(0b011111, 0b0000000000), cmp);
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Bind(SixTen(0b011111, 0b0000000100), tw);
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Bind(SixTen(0b011111, 0b0000001000), subfcx); Bind(SixTen(0b011111, 0b1000001000), subfcx);
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Bind(SixTen(0b011111, 0b0000001010), addcx); Bind(SixTen(0b011111, 0b1000001010), addcx);
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Bind(SixTen(0b011111, 0b0000001011), mulhwux); Bind(SixTen(0b011111, 0b1000001011), mulhwux);
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Bind(SixTen(0b011111, 0b0000010011), mfcr);
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Bind(SixTen(0b011111, 0b0000010100), lwarx);
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Bind(SixTen(0b011111, 0b0000010111), lwzx);
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Bind(SixTen(0b011111, 0b0000011000), slwx);
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Bind(SixTen(0b011111, 0b0000011010), cntlzwx);
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Bind(SixTen(0b011111, 0b0000011100), andx);
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Bind(SixTen(0b011111, 0b0000100000), cmpl);
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Bind(SixTen(0b011111, 0b0000101000), subfx); Bind(SixTen(0b011111, 0b1000101000), subfx);
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Bind(SixTen(0b011111, 0b0000110110), dcbst);
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Bind(SixTen(0b011111, 0b0000110111), lwzux);
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Bind(SixTen(0b011111, 0b0000111100), andcx);
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Bind(SixTen(0b011111, 0b0001001011), mulhwx); Bind(SixTen(0b011111, 0b1001001011), mulhwx);
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Bind(SixTen(0b011111, 0b0001010011), mfmsr);
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Bind(SixTen(0b011111, 0b0001010110), dcbf);
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Bind(SixTen(0b011111, 0b0001010111), lbzx);
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Bind(SixTen(0b011111, 0b0001101000), negx); Bind(SixTen(0b011111, 0b1001101000), negx);
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Bind(SixTen(0b011111, 0b0001110111), lbzux);
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Bind(SixTen(0b011111, 0b0001111100), norx);
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Bind(SixTen(0b011111, 0b0010001000), subfex); Bind(SixTen(0b011111, 0b1010001000), subfex);
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Bind(SixTen(0b011111, 0b0010001010), addex); Bind(SixTen(0b011111, 0b1010001010), addex);
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Bind(SixTen(0b011111, 0b0010010000), mtcrf);
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Bind(SixTen(0b011111, 0b0010010010), mtmsr);
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Bind(SixTen(0b011111, 0b0010010111), stwx);
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Bind(SixTen(0b011111, 0b0010110111), stwux);
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Bind(SixTen(0b011111, 0b0011001000), subfzex); Bind(SixTen(0b011111, 0b1011001000), subfzex);
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Bind(SixTen(0b011111, 0b0011001010), addzex); Bind(SixTen(0b011111, 0b1011001010), addzex);
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Bind(SixTen(0b011111, 0b0011010111), stbx);
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Bind(SixTen(0b011111, 0b0011101000), subfmex); Bind(SixTen(0b011111, 0b1011101000), subfmex);
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Bind(SixTen(0b011111, 0b0011101010), addmex); Bind(SixTen(0b011111, 0b1011101010), addmex);
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Bind(SixTen(0b011111, 0b0011101011), mullwx); Bind(SixTen(0b011111, 0b1011101011), mullwx);
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Bind(SixTen(0b011111, 0b0011110110), dcbtst);
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Bind(SixTen(0b011111, 0b0011110111), stbux);
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Bind(SixTen(0b011111, 0b0100001010), addx); Bind(SixTen(0b011111, 0b1100001010), addx);
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Bind(SixTen(0b011111, 0b0100010110), dcbt);
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Bind(SixTen(0b011111, 0b0100010111), lhzx);
|
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Bind(SixTen(0b011111, 0b0100011100), eqvx);
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Bind(SixTen(0b011111, 0b0100110110), eciwx);
|
||||
Bind(SixTen(0b011111, 0b0100110111), lhzux);
|
||||
Bind(SixTen(0b011111, 0b0100111100), xorx);
|
||||
Bind(SixTen(0b011111, 0b0101010111), lhax);
|
||||
Bind(SixTen(0b011111, 0b0101110011), mftb);
|
||||
Bind(SixTen(0b011111, 0b0101110111), lhaux);
|
||||
Bind(SixTen(0b011111, 0b0110010111), sthx);
|
||||
Bind(SixTen(0b011111, 0b0110011100), orcx);
|
||||
Bind(SixTen(0b011111, 0b0110110110), ecowx);
|
||||
Bind(SixTen(0b011111, 0b0110110111), sthux);
|
||||
Bind(SixTen(0b011111, 0b0110111100), orx);
|
||||
Bind(SixTen(0b011111, 0b0111001011), divwux); Bind(SixTen(0b011111, 0b1111001011), divwux);
|
||||
Bind(SixTen(0b011111, 0b0111010110), dcbi);
|
||||
Bind(SixTen(0b011111, 0b0111011100), nandx);
|
||||
Bind(SixTen(0b011111, 0b0111101011), divwx); Bind(SixTen(0b011111, 0b1111101011), divwx);
|
||||
Bind(SixTen(0b011111, 0b1000000000), mcrxr);
|
||||
Bind(SixTen(0b011111, 0b1000010101), lswx);
|
||||
Bind(SixTen(0b011111, 0b1000010110), lwbrx);
|
||||
Bind(SixTen(0b011111, 0b1000010111), lfsx);
|
||||
Bind(SixTen(0b011111, 0b1000011000), srwx);
|
||||
Bind(SixTen(0b011111, 0b1000110111), lfsux);
|
||||
Bind(SixTen(0b011111, 0b1001010101), lswi);
|
||||
Bind(SixTen(0b011111, 0b1001010110), sync);
|
||||
Bind(SixTen(0b011111, 0b1001010111), lfdx);
|
||||
Bind(SixTen(0b011111, 0b1001110111), lfdux);
|
||||
Bind(SixTen(0b011111, 0b1010010101), stswx);
|
||||
Bind(SixTen(0b011111, 0b1010010110), stwbrx);
|
||||
Bind(SixTen(0b011111, 0b1010010111), stfsx);
|
||||
Bind(SixTen(0b011111, 0b1010110111), stfsux);
|
||||
Bind(SixTen(0b011111, 0b1011010101), stswi);
|
||||
Bind(SixTen(0b011111, 0b1011010111), stfdx);
|
||||
Bind(SixTen(0b011111, 0b1011110111), stfdux);
|
||||
Bind(SixTen(0b011111, 0b1100010110), lhbrx);
|
||||
Bind(SixTen(0b011111, 0b1100011000), srawx);
|
||||
Bind(SixTen(0b011111, 0b1100111000), srawix);
|
||||
Bind(SixTen(0b011111, 0b1101010110), eieio);
|
||||
Bind(SixTen(0b011111, 0b1110010110), sthbrx);
|
||||
Bind(SixTen(0b011111, 0b1110011010), extshx);
|
||||
Bind(SixTen(0b011111, 0b1110111010), extsbx);
|
||||
Bind(SixTen(0b011111, 0b1111010110), icbi);
|
||||
Bind(SixTen(0b011111, 0b1111010111), stfiwx);
|
||||
Bind(SixTen(0b011111, 0b1111110110), dcbz);
|
||||
Bind(SixTen(0b111111, 0b0000000000), fcmpu);
|
||||
Bind(SixTen(0b111111, 0b0000001100), frspx);
|
||||
Bind(SixTen(0b111111, 0b0000001110), fctiwx);
|
||||
Bind(SixTen(0b111111, 0b0000001111), fctiwzx);
|
||||
Bind(SixTen(0b111111, 0b0000100000), fcmpo);
|
||||
Bind(SixTen(0b111111, 0b0000100110), mtfsb1x);
|
||||
Bind(SixTen(0b111111, 0b0000101000), fnegx);
|
||||
Bind(SixTen(0b111111, 0b0001000000), mcrfs);
|
||||
Bind(SixTen(0b111111, 0b0001000110), mtfsb0x);
|
||||
Bind(SixTen(0b111111, 0b0001001000), fmrx);
|
||||
Bind(SixTen(0b111111, 0b0010000110), mtfsfix);
|
||||
Bind(SixTen(0b111111, 0b0010001000), fnabsx);
|
||||
Bind(SixTen(0b111111, 0b0100001000), fabsx);
|
||||
Bind(SixTen(0b111111, 0b1001000111), mffsx);
|
||||
Bind(SixTen(0b111111, 0b1011000111), mtfsfx);
|
||||
Bind(SixTen(0b111111, 0b1100101110), fctidx);
|
||||
Bind(SixTen(0b111111, 0b1100101111), fctidzx);
|
||||
Bind(SixTen(0b111111, 0b1101001110), fcfidx);
|
||||
|
||||
Bind(SixTen(0b011111, 0b0101010011), mfspr); // Flagged as "supervisor and user"?
|
||||
Bind(SixTen(0b011111, 0b0111010011), mtspr); // Flagged as "supervisor and user"?
|
||||
|
||||
BindSupervisorConditional(is32bit, SixTen(0b011111, 0b0011010010), mtsr);
|
||||
BindSupervisorConditional(is32bit, SixTen(0b011111, 0b0011110010), mtsrin);
|
||||
BindSupervisorConditional(is32bit, SixTen(0b011111, 0b1001010011), mfsr);
|
||||
BindSupervisorConditional(is32bit, SixTen(0b011111, 0b1010010011), mfsrin);
|
||||
|
||||
BindSupervisorConditional(is64bit, SixTen(0b011111, 0b0111110010), slbia); // optional
|
||||
|
||||
// The following are all optional; should I record that?
|
||||
BindSupervisor(SixTen(0b011111, 0b0100110010), tlbie);
|
||||
BindSupervisor(SixTen(0b011111, 0b0101110010), tlbia);
|
||||
BindSupervisor(SixTen(0b011111, 0b1000110110), tlbsync);
|
||||
}
|
||||
|
||||
// Third pass: like six-ten except that the top five of the final ten
|
||||
// are reserved (i.e. ignored here).
|
||||
switch(opcode & SixTen(0b111111, 0b11111)) {
|
||||
default: break;
|
||||
|
||||
Bind(SixTen(0b111011, 0b10010), fdivsx);
|
||||
Bind(SixTen(0b111011, 0b10100), fsubsx);
|
||||
Bind(SixTen(0b111011, 0b10101), faddsx);
|
||||
Bind(SixTen(0b111011, 0b11001), fmulsx);
|
||||
Bind(SixTen(0b111011, 0b11100), fmsubsx);
|
||||
Bind(SixTen(0b111011, 0b11101), fmaddsx);
|
||||
Bind(SixTen(0b111011, 0b11110), fnmsubsx);
|
||||
Bind(SixTen(0b111011, 0b11111), fnmaddsx);
|
||||
|
||||
Bind(SixTen(0b111111, 0b10010), fdivx);
|
||||
Bind(SixTen(0b111111, 0b10100), fsubx);
|
||||
Bind(SixTen(0b111111, 0b10101), faddx);
|
||||
Bind(SixTen(0b111111, 0b11001), fmulx);
|
||||
Bind(SixTen(0b111111, 0b11100), fmsubx);
|
||||
Bind(SixTen(0b111111, 0b11101), fmaddx);
|
||||
Bind(SixTen(0b111111, 0b11110), fnmsubx);
|
||||
Bind(SixTen(0b111111, 0b11111), fnmaddx);
|
||||
|
||||
BindConditional(is64bit, SixTen(0b111011, 0b10110), fsqrtsx);
|
||||
BindConditional(is64bit, SixTen(0b111011, 0b11000), fresx);
|
||||
|
||||
// Optional...
|
||||
Bind(SixTen(0b111111, 0b10110), fsqrtx);
|
||||
Bind(SixTen(0b111111, 0b10111), fselx);
|
||||
Bind(SixTen(0b111111, 0b11010), frsqrtex);
|
||||
}
|
||||
|
||||
// stwcx. and stdcx.
|
||||
switch(opcode & 0b111111'00'00000000'000'111111111'1){
|
||||
case 0b011111'00'00000000'00000'0010010110'1: return Instruction(Operation::stwcx_, opcode);
|
||||
case 0b011111'00'00000000'00000'0011010110'1:
|
||||
if(is64bit()) return Instruction(Operation::stdcx_, opcode);
|
||||
return Instruction(opcode);
|
||||
}
|
||||
|
||||
// std and stdu
|
||||
switch(opcode & 0b111111'00'00000000'00000000'000000'11){
|
||||
case 0b111110'00'00000000'00000000'000000'00: return Instruction(Operation::std, opcode);
|
||||
case 0b111110'00'00000000'00000000'000000'01:
|
||||
if(is64bit()) return Instruction(Operation::stdu, opcode);
|
||||
return Instruction(opcode);
|
||||
}
|
||||
|
||||
// sc
|
||||
if((opcode & 0b111111'00'00000000'00000000'000000'1'0) == 0b010001'00'00000000'00000000'000000'1'0) {
|
||||
return Instruction(Operation::sc, opcode);
|
||||
}
|
||||
|
||||
#undef Six
|
||||
#undef SixTen
|
||||
|
||||
#undef Bind
|
||||
#undef BindConditional
|
||||
|
||||
return Instruction(opcode);
|
||||
}
|
||||
58
InstructionSets/PowerPC/Decoder.hpp
Normal file
58
InstructionSets/PowerPC/Decoder.hpp
Normal file
@ -0,0 +1,58 @@
|
||||
//
|
||||
// Decoder.hpp
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 12/30/20.
|
||||
// Copyright © 2020 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#ifndef InstructionSets_PowerPC_Decoder_hpp
|
||||
#define InstructionSets_PowerPC_Decoder_hpp
|
||||
|
||||
#include "Instruction.hpp"
|
||||
|
||||
namespace CPU {
|
||||
namespace Decoder {
|
||||
namespace PowerPC {
|
||||
|
||||
enum class Model {
|
||||
/// i.e. 32-bit, with POWER carry-over instructions.
|
||||
MPC601,
|
||||
/// i.e. 32-bit, no POWER instructions.
|
||||
MPC603,
|
||||
/// i.e. 64-bit.
|
||||
MPC620,
|
||||
};
|
||||
|
||||
/*!
|
||||
Implements PowerPC instruction decoding.
|
||||
|
||||
This is an experimental implementation; it has not yet undergone significant testing.
|
||||
*/
|
||||
struct Decoder {
|
||||
public:
|
||||
Decoder(Model model);
|
||||
|
||||
Instruction decode(uint32_t opcode);
|
||||
|
||||
private:
|
||||
Model model_;
|
||||
|
||||
bool is64bit() const {
|
||||
return model_ == Model::MPC620;
|
||||
}
|
||||
|
||||
bool is32bit() const {
|
||||
return !is64bit();
|
||||
}
|
||||
|
||||
bool is601() const {
|
||||
return model_ == Model::MPC601;
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* InstructionSets_PowerPC_Decoder_hpp */
|
||||
192
InstructionSets/PowerPC/Instruction.hpp
Normal file
192
InstructionSets/PowerPC/Instruction.hpp
Normal file
@ -0,0 +1,192 @@
|
||||
//
|
||||
// Instruction.hpp
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 1/15/21.
|
||||
// Copyright © 2021 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#ifndef InstructionSets_PowerPC_Instruction_h
|
||||
#define InstructionSets_PowerPC_Instruction_h
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
namespace CPU {
|
||||
namespace Decoder {
|
||||
namespace PowerPC {
|
||||
|
||||
enum class Operation: uint8_t {
|
||||
Undefined,
|
||||
|
||||
// These 601-exclusive instructions; a lot of them are carry-overs
|
||||
// from POWER.
|
||||
absx, clcs, divx, divsx, dozx, dozi, lscbxx, maskgx, maskirx, mulx,
|
||||
nabsx, rlmix, rribx, slex, sleqx, sliqx, slliqx, sllqx, slqx,
|
||||
sraiqx, sraqx, srex, sreax, sreqx, sriqx, srliqx, srlqx, srqx,
|
||||
|
||||
// 32- and 64-bit PowerPC instructions.
|
||||
addx, addcx, addex, addi, addic, addic_, addis, addmex, addzex, andx,
|
||||
andcx, andi_, andis_, bx, bcx, bcctrx, bclrx, cmp, cmpi, cmpl, cmpli,
|
||||
cntlzwx, crand, crandc, creqv, crnand, crnor, cror, crorc, crxor, dcbf,
|
||||
dcbst, dcbt, dcbtst, dcbz, divwx, divwux, eciwx, ecowx, eieio, eqvx,
|
||||
extsbx, extshx, fabsx, faddx, faddsx, fcmpo, fcmpu, fctiwx, fctiwzx,
|
||||
fdivx, fdivsx, fmaddx, fmaddsx, fmrx, fmsubx, fmsubsx, fmulx, fmulsx,
|
||||
fnabsx, fnegx, fnmaddx, fnmaddsx, fnmsubx, fnmsubsx, frspx, fsubx, fsubsx,
|
||||
icbi, isync, lbz, lbzu, lbzux, lbzx, lfd, lfdu, lfdux, lfdx, lfs, lfsu,
|
||||
lfsux, lfsx, lha, lhau, lhaux, lhax, lhbrx, lhz, lhzu, lhzux, lhzx, lmw,
|
||||
lswi, lswx, lwarx, lwbrx, lwz, lwzu, lwzux, lwzx, mcrf, mcrfs, mcrxr,
|
||||
mfcr, mffsx, mfmsr, mfspr, mfsr, mfsrin, mtcrf, mtfsb0x, mtfsb1x, mtfsfx,
|
||||
mtfsfix, mtmsr, mtspr, mtsr, mtsrin, mulhwx, mulhwux, mulli, mullwx,
|
||||
nandx, negx, norx, orx, orcx, ori, oris, rfi, rlwimix, rlwinmx, rlwnmx,
|
||||
sc, slwx, srawx, srawix, srwx, stb, stbu, stbux, stbx, stfd, stfdu,
|
||||
stfdux, stfdx, stfs, stfsu, stfsux, stfsx, sth, sthbrx, sthu, sthux, sthx,
|
||||
stmw, stswi, stswx, stw, stwbrx, stwcx_, stwu, stwux, stwx, subfx, subfcx,
|
||||
subfex, subfic, subfmex, subfzex, sync, tw, twi, xorx, xori, xoris, mftb,
|
||||
|
||||
// 32-bit, supervisor level.
|
||||
dcbi,
|
||||
|
||||
// Supervisor, optional.
|
||||
tlbia, tlbie, tlbsync,
|
||||
|
||||
// Optional.
|
||||
fresx, frsqrtex, fselx, fsqrtx, slbia, slbie, stfiwx,
|
||||
|
||||
// 64-bit only PowerPC instructions.
|
||||
cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx, tdi, mulhdux,
|
||||
ldx, sldx, ldux, td, mulhdx, ldarx, stdx, stdux, mulld, lwax, lwaux,
|
||||
sradix, srdx, sradx, extsw, fsqrtsx, std, stdu, stdcx_,
|
||||
};
|
||||
|
||||
/*!
|
||||
Holds a decoded PowerPC instruction.
|
||||
|
||||
Implementation note: because the PowerPC encoding is particularly straightforward,
|
||||
only the operation has been decoded ahead of time; all other fields are decoded on-demand.
|
||||
|
||||
It would be possible to partition the ordering of Operations into user followed by supervisor,
|
||||
eliminating the storage necessary for a flag, but it wouldn't save anything due to alignment.
|
||||
*/
|
||||
struct Instruction {
|
||||
Operation operation = Operation::Undefined;
|
||||
bool is_supervisor = false;
|
||||
uint32_t opcode = 0;
|
||||
|
||||
Instruction() noexcept {}
|
||||
Instruction(uint32_t opcode) noexcept : opcode(opcode) {}
|
||||
Instruction(Operation operation, uint32_t opcode, bool is_supervisor = false) noexcept : operation(operation), is_supervisor(is_supervisor), opcode(opcode) {}
|
||||
|
||||
// Instruction fields are decoded below; naming is a compromise between
|
||||
// Motorola's documentation and IBM's.
|
||||
//
|
||||
// I've dutifully implemented various synonyms with unique entry points,
|
||||
// in order to capture that information here rather than thrusting it upon
|
||||
// the reader of whatever implementation may follow.
|
||||
|
||||
// Currently omitted: OPCD and XO, which I think are unnecessary given that
|
||||
// full decoding has already occurred.
|
||||
|
||||
/// Immediate field used to specify an unsigned 16-bit integer.
|
||||
uint16_t uimm() const { return uint16_t(opcode & 0xffff); }
|
||||
/// Immediate field used to specify a signed 16-bit integer.
|
||||
int16_t simm() const { return int16_t(opcode & 0xffff); }
|
||||
/// Immediate field used to specify a signed 16-bit integer.
|
||||
int16_t d() const { return int16_t(opcode & 0xffff); }
|
||||
/// Immediate field used to specify a signed 14-bit integer [64-bit only].
|
||||
int16_t ds() const { return int16_t(opcode & 0xfffc); }
|
||||
/// Immediate field used as data to be placed into a field in the floating point status and condition register.
|
||||
int32_t imm() const { return (opcode >> 12) & 0xf; }
|
||||
|
||||
/// Specifies the conditions on which to trap.
|
||||
int32_t to() const { return (opcode >> 21) & 0x1f; }
|
||||
|
||||
/// Register source A or destination.
|
||||
uint32_t rA() const { return (opcode >> 16) & 0x1f; }
|
||||
/// Register source B.
|
||||
uint32_t rB() const { return (opcode >> 11) & 0x1f; }
|
||||
/// Register destination.
|
||||
uint32_t rD() const { return (opcode >> 21) & 0x1f; }
|
||||
/// Register source.
|
||||
uint32_t rS() const { return (opcode >> 21) & 0x1f; }
|
||||
|
||||
/// Floating point register source A.
|
||||
uint32_t frA() const { return (opcode >> 16) & 0x1f; }
|
||||
/// Floating point register source B.
|
||||
uint32_t frB() const { return (opcode >> 11) & 0x1f; }
|
||||
/// Floating point register source C.
|
||||
uint32_t frC() const { return (opcode >> 6) & 0x1f; }
|
||||
/// Floating point register source.
|
||||
uint32_t frS() const { return (opcode >> 21) & 0x1f; }
|
||||
/// Floating point register destination.
|
||||
uint32_t frD() const { return (opcode >> 21) & 0x1f; }
|
||||
|
||||
/// Branch conditional options.
|
||||
uint32_t bo() const { return (opcode >> 21) & 0x1f; }
|
||||
/// Source condition register bit for branch conditionals.
|
||||
uint32_t bi() const { return (opcode >> 16) & 0x1f; }
|
||||
/// Branch displacement; provided as already sign extended.
|
||||
int16_t bd() const { return int16_t(opcode & 0xfffc); }
|
||||
|
||||
/// Specifies the first 1 bit of a 32/64-bit mask for rotate operations.
|
||||
uint32_t mb() const { return (opcode >> 6) & 0x1f; }
|
||||
/// Specifies the first 1 bit of a 32/64-bit mask for rotate operations.
|
||||
uint32_t me() const { return (opcode >> 1) & 0x1f; }
|
||||
|
||||
/// Condition register source bit A.
|
||||
uint32_t crbA() const { return (opcode >> 16) & 0x1f; }
|
||||
/// Condition register source bit B.
|
||||
uint32_t crbB() const { return (opcode >> 11) & 0x1f; }
|
||||
/// Condition register (or floating point status & condition register) destination bit.
|
||||
uint32_t crbD() const { return (opcode >> 21) & 0x1f; }
|
||||
|
||||
/// Condition register (or floating point status & condition register) destination field.
|
||||
uint32_t crfD() const { return (opcode >> 23) & 0x07; }
|
||||
/// Condition register (or floating point status & condition register) source field.
|
||||
uint32_t crfS() const { return (opcode >> 18) & 0x07; }
|
||||
|
||||
/// Mask identifying fields to be updated by mtcrf.
|
||||
uint32_t crm() const { return (opcode >> 12) & 0xff; }
|
||||
|
||||
/// Mask identifying fields to be updated by mtfsf.
|
||||
uint32_t fm() const { return (opcode >> 17) & 0xff; }
|
||||
|
||||
/// Specifies the number of bytes to move in an immediate string load or store.
|
||||
uint32_t nb() const { return (opcode >> 11) & 0x1f; }
|
||||
|
||||
/// Specifies a shift amount.
|
||||
/// TODO: possibly bit 30 is also used in 64-bit mode, find out.
|
||||
uint32_t sh() const { return (opcode >> 11) & 0x1f; }
|
||||
|
||||
/// Specifies one of the 16 segment registers [32-bit only].
|
||||
uint32_t sr() const { return (opcode >> 16) & 0xf; }
|
||||
|
||||
/// A 24-bit signed number; provided as already sign extended.
|
||||
int32_t li() const {
|
||||
constexpr uint32_t extensions[2] = {
|
||||
0x0000'0000,
|
||||
0xfc00'0000
|
||||
};
|
||||
const uint32_t value = (opcode & 0x03ff'fffc) | extensions[(opcode >> 25) & 1];
|
||||
return int32_t(value);
|
||||
}
|
||||
|
||||
/// Absolute address bit; @c 0 or @c non-0.
|
||||
uint32_t aa() const { return opcode & 0x02; }
|
||||
/// Link bit; @c 0 or @c non-0.
|
||||
uint32_t lk() const { return opcode & 0x01; }
|
||||
/// Record bit; @c 0 or @c non-0.
|
||||
uint32_t rc() const { return opcode & 0x01; }
|
||||
/// Whether to compare 32-bit or 64-bit numbers [for 64-bit implementations only]; @c 0 or @c non-0.
|
||||
uint32_t l() const { return opcode & 0x200000; }
|
||||
/// Enables setting of OV and SO in the XER; @c 0 or @c non-0.
|
||||
uint32_t oe() const { return opcode & 0x800; }
|
||||
};
|
||||
|
||||
// Sanity check on Instruction size.
|
||||
static_assert(sizeof(Instruction) <= 8);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* InstructionSets_PowerPC_Instruction_h */
|
||||
54
InstructionSets/README.md
Normal file
54
InstructionSets/README.md
Normal file
@ -0,0 +1,54 @@
|
||||
# Instruction Sets
|
||||
|
||||
## Decoders
|
||||
|
||||
A decoder extracts fully-decoded instructions from a data stream for its associated architecture.
|
||||
|
||||
The meaning of 'fully-decoded' is flexible but it means that a caller can easily discern at least:
|
||||
* the operation in use;
|
||||
* its addressing mode; and
|
||||
* relevant registers.
|
||||
|
||||
It may be assumed that callers will have access to the original data stream for immediate values, if it is sensible to do so.
|
||||
|
||||
In deciding what to expose, what to store ahead of time and what to obtain just-in-time a decoder should have an eye on two principal consumers:
|
||||
1. disassemblers; and
|
||||
2. instruction executors.
|
||||
|
||||
It may also be reasonable to make allowances for bus-centric CPU emulators, but those will be tightly coupled to specific decoders so no general rules need apply.
|
||||
|
||||
Disassemblers are likely to decode an instruction, output it, and then immediately forget about it.
|
||||
|
||||
Instruction executors may opt to cache decoded instructions to reduce recurrent costs, but will always be dealing with an actual instruction stream. The chance of caching means that decoded instructions should seek to be small. If helpful then a decoder might prefer to return a `std::pair` or similar of ephemeral information and stuff that it is meaningful to store.
|
||||
|
||||
## Likely Interfaces
|
||||
|
||||
These examples assume that the processor itself doesn't hold any state that affects instruction parsing. Whether processors with such state offer more than one decoder or take state as an argument will be a question of measure and effect.
|
||||
|
||||
### Fixed-size instruction words
|
||||
|
||||
If the instructions are a fixed size, the decoder can provide what is functionally a simple lookup, whether implemented as such or not:
|
||||
|
||||
Instruction decode(word_type instruction) { ... }
|
||||
|
||||
For now I have preferred not to make this a simple constructor on `Instruction` because I'm reserving the option of switching to an ephemeral/permanent split in what's returned. More consideration needs to be applied here.
|
||||
|
||||
### Variable-size instruction words
|
||||
|
||||
If instructions are a variable size, the decoder should maintain internal state such that it can be provided with fragments of instructions until a full decoding has occurred — this avoids an assumption that all source bytes will always be laid out linearly in memory.
|
||||
|
||||
A sample interface:
|
||||
|
||||
std::pair<int, Instruction> decode(word_type *stream, size_t length) { ... }
|
||||
|
||||
In this sample the returned pair provides an `int` size that is one of:
|
||||
* a positive number, indicating a completed decoding that consumed that many `word_type`s; or
|
||||
* a negative number, indicating the [negatived] minimum number of `word_type`s that the caller should try to get hold of before calling `decode` again.
|
||||
|
||||
A caller is permitted to react in any way it prefers to negative numbers; they're a hint potentially to reduce calling overhead only. A size of `0` would be taken to have the same meaning as a size of `-1`.
|
||||
|
||||
## Tying Decoders into Instruction Executors
|
||||
|
||||
It is assumed that disassemblers and bus-centric CPU emulators have limited generic functionality; for executors it is assumed that a processor-specific instruction fetcher and a dispatcher will be provided to couple with the decoder.
|
||||
|
||||
Therefore decoders should adopt whatever interface is most natural; the expected uses information above is to provide a motivation for the scope of responsibilities and hints as to likely performance objectives only. Beyond requiring that decoded instructions be a tangible struct or class, it is not intended to be prescriptive as to form or interface.
|
||||
625
InstructionSets/x86/Decoder.cpp
Normal file
625
InstructionSets/x86/Decoder.cpp
Normal file
@ -0,0 +1,625 @@
|
||||
//
|
||||
// x86.cpp
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 1/1/21.
|
||||
// Copyright © 2021 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#include "Decoder.hpp"
|
||||
|
||||
#include <algorithm>
|
||||
#include <cassert>
|
||||
#include <utility>
|
||||
|
||||
using namespace CPU::Decoder::x86;
|
||||
|
||||
// Only 8086 is suppoted for now.
|
||||
Decoder::Decoder(Model) {}
|
||||
|
||||
std::pair<int, CPU::Decoder::x86::Instruction> Decoder::decode(const uint8_t *source, size_t length) {
|
||||
const uint8_t *const end = source + length;
|
||||
|
||||
// MARK: - Prefixes (if present) and the opcode.
|
||||
|
||||
/// Helper macro for those that follow.
|
||||
#define SetOpSrcDestSize(op, src, dest, size) \
|
||||
operation_ = Operation::op; \
|
||||
source_ = Source::src; \
|
||||
destination_ = Source::dest; \
|
||||
operation_size_ = size
|
||||
|
||||
/// Covers anything which is complete as soon as the opcode is encountered.
|
||||
#define Complete(op, src, dest, size) \
|
||||
SetOpSrcDestSize(op, src, dest, size); \
|
||||
phase_ = Phase::ReadyToPost
|
||||
|
||||
/// Handles instructions of the form rr, kk and rr, jjkk, i.e. a destination register plus an operand.
|
||||
#define RegData(op, dest, size) \
|
||||
SetOpSrcDestSize(op, DirectAddress, dest, size); \
|
||||
source_ = Source::Immediate; \
|
||||
operand_size_ = size; \
|
||||
phase_ = Phase::AwaitingDisplacementOrOperand
|
||||
|
||||
/// Handles instructions of the form Ax, jjkk where the latter is implicitly an address.
|
||||
#define RegAddr(op, dest, op_size, addr_size) \
|
||||
SetOpSrcDestSize(op, DirectAddress, dest, op_size); \
|
||||
operand_size_ = addr_size; \
|
||||
phase_ = Phase::AwaitingDisplacementOrOperand
|
||||
|
||||
/// Handles instructions of the form jjkk, Ax where the former is implicitly an address.
|
||||
#define AddrReg(op, source, op_size, addr_size) \
|
||||
SetOpSrcDestSize(op, source, DirectAddress, op_size); \
|
||||
operand_size_ = addr_size; \
|
||||
destination_ = Source::DirectAddress; \
|
||||
phase_ = Phase::AwaitingDisplacementOrOperand
|
||||
|
||||
/// Covers both `mem/reg, reg` and `reg, mem/reg`.
|
||||
#define MemRegReg(op, format, size) \
|
||||
operation_ = Operation::op; \
|
||||
phase_ = Phase::ModRegRM; \
|
||||
modregrm_format_ = ModRegRMFormat::format; \
|
||||
operand_size_ = 0; \
|
||||
operation_size_ = size
|
||||
|
||||
/// Handles JO, JNO, JB, etc — jumps with a single byte displacement.
|
||||
#define Jump(op) \
|
||||
operation_ = Operation::op; \
|
||||
phase_ = Phase::AwaitingDisplacementOrOperand; \
|
||||
displacement_size_ = 1
|
||||
|
||||
/// Handles far CALL and far JMP — fixed four byte operand operations.
|
||||
#define Far(op) \
|
||||
operation_ = Operation::op; \
|
||||
phase_ = Phase::AwaitingDisplacementOrOperand; \
|
||||
operand_size_ = 4; \
|
||||
|
||||
while(phase_ == Phase::Instruction && source != end) {
|
||||
// Retain the instruction byte, in case additional decoding is deferred
|
||||
// to the ModRegRM byte.
|
||||
instr_ = *source;
|
||||
++source;
|
||||
++consumed_;
|
||||
|
||||
switch(instr_) {
|
||||
default: {
|
||||
const auto result = std::make_pair(consumed_, Instruction());
|
||||
reset_parsing();
|
||||
return result;
|
||||
}
|
||||
|
||||
#define PartialBlock(start, operation) \
|
||||
case start + 0x00: MemRegReg(operation, MemReg_Reg, 1); break; \
|
||||
case start + 0x01: MemRegReg(operation, MemReg_Reg, 2); break; \
|
||||
case start + 0x02: MemRegReg(operation, Reg_MemReg, 1); break; \
|
||||
case start + 0x03: MemRegReg(operation, Reg_MemReg, 2); break; \
|
||||
case start + 0x04: RegData(operation, AL, 1); break; \
|
||||
case start + 0x05: RegData(operation, AX, 2)
|
||||
|
||||
PartialBlock(0x00, ADD); break;
|
||||
case 0x06: Complete(PUSH, ES, None, 2); break;
|
||||
case 0x07: Complete(POP, None, ES, 2); break;
|
||||
|
||||
PartialBlock(0x08, OR); break;
|
||||
case 0x0e: Complete(PUSH, CS, None, 2); break;
|
||||
|
||||
PartialBlock(0x10, ADC); break;
|
||||
case 0x16: Complete(PUSH, SS, None, 2); break;
|
||||
case 0x17: Complete(POP, None, SS, 2); break;
|
||||
|
||||
PartialBlock(0x18, SBB); break;
|
||||
case 0x1e: Complete(PUSH, DS, None, 2); break;
|
||||
case 0x1f: Complete(POP, None, DS, 2); break;
|
||||
|
||||
PartialBlock(0x20, AND); break;
|
||||
case 0x26: segment_override_ = Source::ES; break;
|
||||
case 0x27: Complete(DAA, AL, AL, 1); break;
|
||||
|
||||
PartialBlock(0x28, SUB); break;
|
||||
case 0x2e: segment_override_ = Source::CS; break;
|
||||
case 0x2f: Complete(DAS, AL, AL, 1); break;
|
||||
|
||||
PartialBlock(0x30, XOR); break;
|
||||
case 0x36: segment_override_ = Source::SS; break;
|
||||
case 0x37: Complete(AAA, AL, AX, 1); break;
|
||||
|
||||
PartialBlock(0x38, CMP); break;
|
||||
case 0x3e: segment_override_ = Source::DS; break;
|
||||
case 0x3f: Complete(AAS, AL, AX, 1); break;
|
||||
|
||||
#undef PartialBlock
|
||||
|
||||
#define RegisterBlock(start, operation) \
|
||||
case start + 0x00: Complete(operation, AX, AX, 2); break; \
|
||||
case start + 0x01: Complete(operation, CX, CX, 2); break; \
|
||||
case start + 0x02: Complete(operation, DX, DX, 2); break; \
|
||||
case start + 0x03: Complete(operation, BX, BX, 2); break; \
|
||||
case start + 0x04: Complete(operation, SP, SP, 2); break; \
|
||||
case start + 0x05: Complete(operation, BP, BP, 2); break; \
|
||||
case start + 0x06: Complete(operation, SI, SI, 2); break; \
|
||||
case start + 0x07: Complete(operation, DI, DI, 2)
|
||||
|
||||
RegisterBlock(0x40, INC); break;
|
||||
RegisterBlock(0x48, DEC); break;
|
||||
RegisterBlock(0x50, PUSH); break;
|
||||
RegisterBlock(0x58, POP); break;
|
||||
|
||||
#undef RegisterBlock
|
||||
|
||||
// 0x60–0x6f: not used.
|
||||
|
||||
case 0x70: Jump(JO); break;
|
||||
case 0x71: Jump(JNO); break;
|
||||
case 0x72: Jump(JB); break;
|
||||
case 0x73: Jump(JNB); break;
|
||||
case 0x74: Jump(JE); break;
|
||||
case 0x75: Jump(JNE); break;
|
||||
case 0x76: Jump(JBE); break;
|
||||
case 0x77: Jump(JNBE); break;
|
||||
case 0x78: Jump(JS); break;
|
||||
case 0x79: Jump(JNS); break;
|
||||
case 0x7a: Jump(JP); break;
|
||||
case 0x7b: Jump(JNP); break;
|
||||
case 0x7c: Jump(JL); break;
|
||||
case 0x7d: Jump(JNL); break;
|
||||
case 0x7e: Jump(JLE); break;
|
||||
case 0x7f: Jump(JNLE); break;
|
||||
|
||||
case 0x80: MemRegReg(Invalid, MemRegADD_to_CMP, 1); break;
|
||||
case 0x81: MemRegReg(Invalid, MemRegADD_to_CMP, 2); break;
|
||||
case 0x82: MemRegReg(Invalid, MemRegADC_to_CMP, 1); break;
|
||||
case 0x83: MemRegReg(Invalid, MemRegADC_to_CMP, 2); break;
|
||||
|
||||
case 0x84: MemRegReg(TEST, MemReg_Reg, 1); break;
|
||||
case 0x85: MemRegReg(TEST, MemReg_Reg, 2); break;
|
||||
case 0x86: MemRegReg(XCHG, Reg_MemReg, 1); break;
|
||||
case 0x87: MemRegReg(XCHG, Reg_MemReg, 2); break;
|
||||
case 0x88: MemRegReg(MOV, MemReg_Reg, 1); break;
|
||||
case 0x89: MemRegReg(MOV, MemReg_Reg, 2); break;
|
||||
case 0x8a: MemRegReg(MOV, Reg_MemReg, 1); break;
|
||||
case 0x8b: MemRegReg(MOV, Reg_MemReg, 2); break;
|
||||
// 0x8c: not used.
|
||||
case 0x8d: MemRegReg(LEA, Reg_MemReg, 2); break;
|
||||
case 0x8e: MemRegReg(MOV, SegReg, 2); break;
|
||||
case 0x8f: MemRegReg(POP, MemRegPOP, 2); break;
|
||||
|
||||
case 0x90: Complete(NOP, None, None, 0); break; // Or XCHG AX, AX?
|
||||
case 0x91: Complete(XCHG, AX, CX, 2); break;
|
||||
case 0x92: Complete(XCHG, AX, DX, 2); break;
|
||||
case 0x93: Complete(XCHG, AX, BX, 2); break;
|
||||
case 0x94: Complete(XCHG, AX, SP, 2); break;
|
||||
case 0x95: Complete(XCHG, AX, BP, 2); break;
|
||||
case 0x96: Complete(XCHG, AX, SI, 2); break;
|
||||
case 0x97: Complete(XCHG, AX, DI, 2); break;
|
||||
|
||||
case 0x98: Complete(CBW, AL, AH, 1); break;
|
||||
case 0x99: Complete(CWD, AX, DX, 2); break;
|
||||
case 0x9a: Far(CALLF); break;
|
||||
case 0x9b: Complete(WAIT, None, None, 0); break;
|
||||
case 0x9c: Complete(PUSHF, None, None, 2); break;
|
||||
case 0x9d: Complete(POPF, None, None, 2); break;
|
||||
case 0x9e: Complete(SAHF, None, None, 1); break;
|
||||
case 0x9f: Complete(LAHF, None, None, 1); break;
|
||||
|
||||
case 0xa0: RegAddr(MOV, AL, 1, 1); break;
|
||||
case 0xa1: RegAddr(MOV, AX, 2, 2); break;
|
||||
case 0xa2: AddrReg(MOV, AL, 1, 1); break;
|
||||
case 0xa3: AddrReg(MOV, AX, 2, 2); break;
|
||||
|
||||
case 0xa4: Complete(MOVS, None, None, 1); break;
|
||||
case 0xa5: Complete(MOVS, None, None, 2); break;
|
||||
case 0xa6: Complete(CMPS, None, None, 1); break;
|
||||
case 0xa7: Complete(CMPS, None, None, 2); break;
|
||||
case 0xa8: RegData(TEST, AL, 1); break;
|
||||
case 0xa9: RegData(TEST, AX, 2); break;
|
||||
case 0xaa: Complete(STOS, None, None, 1); break;
|
||||
case 0xab: Complete(STOS, None, None, 2); break;
|
||||
case 0xac: Complete(LODS, None, None, 1); break;
|
||||
case 0xad: Complete(LODS, None, None, 2); break;
|
||||
case 0xae: Complete(SCAS, None, None, 1); break;
|
||||
case 0xaf: Complete(SCAS, None, None, 2); break;
|
||||
|
||||
case 0xb0: RegData(MOV, AL, 1); break;
|
||||
case 0xb1: RegData(MOV, CL, 1); break;
|
||||
case 0xb2: RegData(MOV, DL, 1); break;
|
||||
case 0xb3: RegData(MOV, BL, 1); break;
|
||||
case 0xb4: RegData(MOV, AH, 1); break;
|
||||
case 0xb5: RegData(MOV, CH, 1); break;
|
||||
case 0xb6: RegData(MOV, DH, 1); break;
|
||||
case 0xb7: RegData(MOV, BH, 1); break;
|
||||
case 0xb8: RegData(MOV, AX, 2); break;
|
||||
case 0xb9: RegData(MOV, CX, 2); break;
|
||||
case 0xba: RegData(MOV, DX, 2); break;
|
||||
case 0xbb: RegData(MOV, BX, 2); break;
|
||||
case 0xbc: RegData(MOV, SP, 2); break;
|
||||
case 0xbd: RegData(MOV, BP, 2); break;
|
||||
case 0xbe: RegData(MOV, SI, 2); break;
|
||||
case 0xbf: RegData(MOV, DI, 2); break;
|
||||
|
||||
case 0xc2: RegData(RETN, None, 2); break;
|
||||
case 0xc3: Complete(RETN, None, None, 2); break;
|
||||
case 0xc4: MemRegReg(LES, Reg_MemReg, 2); break;
|
||||
case 0xc5: MemRegReg(LDS, Reg_MemReg, 2); break;
|
||||
case 0xc6: MemRegReg(MOV, MemRegMOV, 1); break;
|
||||
case 0xc7: MemRegReg(MOV, MemRegMOV, 2); break;
|
||||
|
||||
case 0xca: RegData(RETF, None, 2); break;
|
||||
case 0xcb: Complete(RETF, None, None, 4); break;
|
||||
|
||||
case 0xcc: Complete(INT3, None, None, 0); break;
|
||||
case 0xcd: RegData(INT, None, 1); break;
|
||||
case 0xce: Complete(INTO, None, None, 0); break;
|
||||
case 0xcf: Complete(IRET, None, None, 0); break;
|
||||
|
||||
case 0xd0: case 0xd1:
|
||||
phase_ = Phase::ModRegRM;
|
||||
modregrm_format_ = ModRegRMFormat::MemRegROL_to_SAR;
|
||||
operation_size_ = 1 + (instr_ & 1);
|
||||
source_ = Source::Immediate;
|
||||
operand_ = 1;
|
||||
break;
|
||||
case 0xd2: case 0xd3:
|
||||
phase_ = Phase::ModRegRM;
|
||||
modregrm_format_ = ModRegRMFormat::MemRegROL_to_SAR;
|
||||
operation_size_ = 1 + (instr_ & 1);
|
||||
source_ = Source::CL;
|
||||
break;
|
||||
case 0xd4: RegData(AAM, AX, 1); break;
|
||||
case 0xd5: RegData(AAD, AX, 1); break;
|
||||
|
||||
case 0xd7: Complete(XLAT, None, None, 1); break;
|
||||
|
||||
case 0xd8: MemRegReg(ESC, MemReg_Reg, 0); break;
|
||||
case 0xd9: MemRegReg(ESC, MemReg_Reg, 0); break;
|
||||
case 0xda: MemRegReg(ESC, MemReg_Reg, 0); break;
|
||||
case 0xdb: MemRegReg(ESC, MemReg_Reg, 0); break;
|
||||
case 0xdc: MemRegReg(ESC, MemReg_Reg, 0); break;
|
||||
case 0xdd: MemRegReg(ESC, MemReg_Reg, 0); break;
|
||||
case 0xde: MemRegReg(ESC, MemReg_Reg, 0); break;
|
||||
case 0xdf: MemRegReg(ESC, MemReg_Reg, 0); break;
|
||||
|
||||
case 0xe0: Jump(LOOPNE); break;
|
||||
case 0xe1: Jump(LOOPE); break;
|
||||
case 0xe2: Jump(LOOP); break;
|
||||
case 0xe3: Jump(JPCX); break;
|
||||
|
||||
case 0xe4: RegAddr(IN, AL, 1, 1); break;
|
||||
case 0xe5: RegAddr(IN, AX, 2, 1); break;
|
||||
case 0xe6: AddrReg(OUT, AL, 1, 1); break;
|
||||
case 0xe7: AddrReg(OUT, AX, 2, 1); break;
|
||||
|
||||
case 0xe8: RegData(CALLD, None, 2); break;
|
||||
case 0xe9: RegData(JMPN, None, 2); break;
|
||||
case 0xea: Far(JMPF); break;
|
||||
case 0xeb: Jump(JMPN); break;
|
||||
|
||||
case 0xec: Complete(IN, DX, AL, 1); break;
|
||||
case 0xed: Complete(IN, DX, AX, 1); break;
|
||||
case 0xee: Complete(OUT, AL, DX, 1); break;
|
||||
case 0xef: Complete(OUT, AX, DX, 2); break;
|
||||
|
||||
case 0xf4: Complete(HLT, None, None, 1); break;
|
||||
case 0xf5: Complete(CMC, None, None, 1); break;
|
||||
case 0xf6: MemRegReg(Invalid, MemRegTEST_to_IDIV, 1); break;
|
||||
case 0xf7: MemRegReg(Invalid, MemRegTEST_to_IDIV, 2); break;
|
||||
|
||||
case 0xf8: Complete(CLC, None, None, 1); break;
|
||||
case 0xf9: Complete(STC, None, None, 1); break;
|
||||
case 0xfa: Complete(CLI, None, None, 1); break;
|
||||
case 0xfb: Complete(STI, None, None, 1); break;
|
||||
case 0xfc: Complete(CLD, None, None, 1); break;
|
||||
case 0xfd: Complete(STD, None, None, 1); break;
|
||||
|
||||
case 0xfe: MemRegReg(Invalid, MemRegINC_DEC, 1); break;
|
||||
case 0xff: MemRegReg(Invalid, MemRegINC_to_PUSH, 1); break;
|
||||
|
||||
// Other prefix bytes.
|
||||
case 0xf0: lock_ = true; break;
|
||||
case 0xf2: repetition_ = Repetition::RepNE; break;
|
||||
case 0xf3: repetition_ = Repetition::RepE; break;
|
||||
}
|
||||
}
|
||||
|
||||
#undef Far
|
||||
#undef Jump
|
||||
#undef MemRegReg
|
||||
#undef AddrReg
|
||||
#undef RegAddr
|
||||
#undef RegData
|
||||
#undef Complete
|
||||
#undef SetOpSrcDestSize
|
||||
|
||||
// MARK: - ModRegRM byte, if any.
|
||||
|
||||
if(phase_ == Phase::ModRegRM && source != end) {
|
||||
const uint8_t mod = *source >> 6; // i.e. mode.
|
||||
const uint8_t reg = (*source >> 3) & 7; // i.e. register.
|
||||
const uint8_t rm = *source & 7; // i.e. register/memory.
|
||||
++source;
|
||||
++consumed_;
|
||||
|
||||
Source memreg;
|
||||
constexpr Source reg_table[3][8] = {
|
||||
{},
|
||||
{
|
||||
Source::AL, Source::CL, Source::DL, Source::BL,
|
||||
Source::AH, Source::CH, Source::DH, Source::BH,
|
||||
}, {
|
||||
Source::AX, Source::CX, Source::DX, Source::BX,
|
||||
Source::SP, Source::BP, Source::SI, Source::DI,
|
||||
}
|
||||
};
|
||||
switch(mod) {
|
||||
case 0: {
|
||||
constexpr Source rm_table[8] = {
|
||||
Source::IndBXPlusSI, Source::IndBXPlusDI,
|
||||
Source::IndBPPlusSI, Source::IndBPPlusDI,
|
||||
Source::IndSI, Source::IndDI,
|
||||
Source::DirectAddress, Source::IndBX,
|
||||
};
|
||||
memreg = rm_table[rm];
|
||||
} break;
|
||||
|
||||
default: {
|
||||
constexpr Source rm_table[8] = {
|
||||
Source::IndBXPlusSI, Source::IndBXPlusDI,
|
||||
Source::IndBPPlusSI, Source::IndBPPlusDI,
|
||||
Source::IndSI, Source::IndDI,
|
||||
Source::IndBP, Source::IndBX,
|
||||
};
|
||||
memreg = rm_table[rm];
|
||||
|
||||
displacement_size_ = 1 + (mod == 2);
|
||||
} break;
|
||||
|
||||
// Other operand is just a register.
|
||||
case 3:
|
||||
memreg = reg_table[operation_size_][rm];
|
||||
|
||||
// LES and LDS accept a memory argument only, not a register.
|
||||
if(operation_ == Operation::LES || operation_ == Operation::LDS) {
|
||||
const auto result = std::make_pair(consumed_, Instruction());
|
||||
reset_parsing();
|
||||
return result;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
switch(modregrm_format_) {
|
||||
case ModRegRMFormat::Reg_MemReg:
|
||||
case ModRegRMFormat::MemReg_Reg: {
|
||||
if(modregrm_format_ == ModRegRMFormat::Reg_MemReg) {
|
||||
source_ = memreg;
|
||||
destination_ = reg_table[operation_size_][reg];
|
||||
} else {
|
||||
source_ = reg_table[operation_size_][reg];
|
||||
destination_ = memreg;
|
||||
}
|
||||
} break;
|
||||
|
||||
case ModRegRMFormat::MemRegTEST_to_IDIV:
|
||||
source_ = destination_ = memreg;
|
||||
|
||||
switch(reg) {
|
||||
default: {
|
||||
const auto result = std::make_pair(consumed_, Instruction());
|
||||
reset_parsing();
|
||||
return result;
|
||||
}
|
||||
|
||||
case 0: operation_ = Operation::TEST; break;
|
||||
case 2: operation_ = Operation::NOT; break;
|
||||
case 3: operation_ = Operation::NEG; break;
|
||||
case 4: operation_ = Operation::MUL; break;
|
||||
case 5: operation_ = Operation::IMUL; break;
|
||||
case 6: operation_ = Operation::DIV; break;
|
||||
case 7: operation_ = Operation::IDIV; break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ModRegRMFormat::SegReg: {
|
||||
source_ = memreg;
|
||||
|
||||
constexpr Source seg_table[4] = {
|
||||
Source::ES, Source::CS,
|
||||
Source::SS, Source::DS,
|
||||
};
|
||||
|
||||
if(reg & 4) {
|
||||
const auto result = std::make_pair(consumed_, Instruction());
|
||||
reset_parsing();
|
||||
return result;
|
||||
}
|
||||
|
||||
destination_ = seg_table[reg];
|
||||
} break;
|
||||
|
||||
case ModRegRMFormat::MemRegROL_to_SAR:
|
||||
destination_ = memreg;
|
||||
|
||||
switch(reg) {
|
||||
default: {
|
||||
const auto result = std::make_pair(consumed_, Instruction());
|
||||
reset_parsing();
|
||||
return result;
|
||||
}
|
||||
|
||||
case 0: operation_ = Operation::ROL; break;
|
||||
case 2: operation_ = Operation::ROR; break;
|
||||
case 3: operation_ = Operation::RCL; break;
|
||||
case 4: operation_ = Operation::RCR; break;
|
||||
case 5: operation_ = Operation::SAL; break;
|
||||
case 6: operation_ = Operation::SHR; break;
|
||||
case 7: operation_ = Operation::SAR; break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ModRegRMFormat::MemRegINC_DEC:
|
||||
source_ = destination_ = memreg;
|
||||
|
||||
switch(reg) {
|
||||
default: {
|
||||
const auto result = std::make_pair(consumed_, Instruction());
|
||||
reset_parsing();
|
||||
return result;
|
||||
}
|
||||
|
||||
case 0: operation_ = Operation::INC; break;
|
||||
case 1: operation_ = Operation::DEC; break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ModRegRMFormat::MemRegINC_to_PUSH:
|
||||
source_ = destination_ = memreg;
|
||||
|
||||
switch(reg) {
|
||||
default: {
|
||||
const auto result = std::make_pair(consumed_, Instruction());
|
||||
reset_parsing();
|
||||
return result;
|
||||
}
|
||||
|
||||
case 0: operation_ = Operation::INC; break;
|
||||
case 1: operation_ = Operation::DEC; break;
|
||||
case 2: operation_ = Operation::CALLN; break;
|
||||
case 3:
|
||||
operation_ = Operation::CALLF;
|
||||
operand_size_ = 4;
|
||||
source_ = Source::Immediate;
|
||||
break;
|
||||
case 4: operation_ = Operation::JMPN; break;
|
||||
case 5:
|
||||
operation_ = Operation::JMPF;
|
||||
operand_size_ = 4;
|
||||
source_ = Source::Immediate;
|
||||
break;
|
||||
case 6: operation_ = Operation::PUSH; break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ModRegRMFormat::MemRegPOP:
|
||||
source_ = destination_ = memreg;
|
||||
|
||||
if(reg != 0) {
|
||||
reset_parsing();
|
||||
return std::make_pair(consumed_, Instruction());
|
||||
}
|
||||
break;
|
||||
|
||||
case ModRegRMFormat::MemRegMOV:
|
||||
source_ = Source::Immediate;
|
||||
destination_ = memreg;
|
||||
operand_size_ = operation_size_;
|
||||
break;
|
||||
|
||||
case ModRegRMFormat::MemRegADD_to_CMP:
|
||||
destination_ = memreg;
|
||||
operand_size_ = operation_size_;
|
||||
|
||||
switch(reg) {
|
||||
default: operation_ = Operation::ADD; break;
|
||||
case 1: operation_ = Operation::OR; break;
|
||||
case 2: operation_ = Operation::ADC; break;
|
||||
case 3: operation_ = Operation::SBB; break;
|
||||
case 4: operation_ = Operation::AND; break;
|
||||
case 5: operation_ = Operation::SUB; break;
|
||||
case 6: operation_ = Operation::XOR; break;
|
||||
case 7: operation_ = Operation::CMP; break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ModRegRMFormat::MemRegADC_to_CMP:
|
||||
destination_ = memreg;
|
||||
source_ = Source::Immediate;
|
||||
operand_size_ = 1; // ... and always 1; it'll be sign extended if
|
||||
// the operation requires it.
|
||||
|
||||
switch(reg) {
|
||||
default: {
|
||||
const auto result = std::make_pair(consumed_, Instruction());
|
||||
reset_parsing();
|
||||
return result;
|
||||
}
|
||||
|
||||
case 0: operation_ = Operation::ADD; break;
|
||||
case 2: operation_ = Operation::ADC; break;
|
||||
case 3: operation_ = Operation::SBB; break;
|
||||
case 5: operation_ = Operation::SUB; break;
|
||||
case 7: operation_ = Operation::CMP; break;
|
||||
}
|
||||
break;
|
||||
|
||||
default: assert(false);
|
||||
}
|
||||
|
||||
phase_ = (displacement_size_ + operand_size_) ? Phase::AwaitingDisplacementOrOperand : Phase::ReadyToPost;
|
||||
}
|
||||
|
||||
// MARK: - Displacement and operand.
|
||||
|
||||
if(phase_ == Phase::AwaitingDisplacementOrOperand && source != end) {
|
||||
const int required_bytes = displacement_size_ + operand_size_;
|
||||
|
||||
const int outstanding_bytes = required_bytes - operand_bytes_;
|
||||
const int bytes_to_consume = std::min(int(end - source), outstanding_bytes);
|
||||
|
||||
// TODO: I can surely do better than this?
|
||||
for(int c = 0; c < bytes_to_consume; c++) {
|
||||
inward_data_ = (inward_data_ >> 8) | (uint64_t(source[0]) << 56);
|
||||
++source;
|
||||
}
|
||||
|
||||
consumed_ += bytes_to_consume;
|
||||
operand_bytes_ += bytes_to_consume;
|
||||
|
||||
if(bytes_to_consume == outstanding_bytes) {
|
||||
phase_ = Phase::ReadyToPost;
|
||||
|
||||
switch(operand_size_) {
|
||||
default: operand_ = 0; break;
|
||||
case 1:
|
||||
operand_ = inward_data_ >> 56; inward_data_ <<= 8;
|
||||
|
||||
// Sign extend if a single byte operand is feeding a two-byte instruction.
|
||||
if(operation_size_ == 2 && operation_ != Operation::IN && operation_ != Operation::OUT) {
|
||||
operand_ |= (operand_ & 0x80) ? 0xff00 : 0x0000;
|
||||
}
|
||||
break;
|
||||
case 4: displacement_size_ = 2; [[fallthrough]];
|
||||
case 2: operand_ = inward_data_ >> 48; inward_data_ <<= 16; break;
|
||||
break;
|
||||
}
|
||||
switch(displacement_size_) {
|
||||
default: displacement_ = 0; break;
|
||||
case 1: displacement_ = int8_t(inward_data_ >> 56); break;
|
||||
case 2: displacement_ = int16_t(inward_data_ >> 48); break;
|
||||
}
|
||||
} else {
|
||||
// Provide a genuine measure of further bytes required.
|
||||
return std::make_pair(-(outstanding_bytes - bytes_to_consume), Instruction());
|
||||
}
|
||||
}
|
||||
|
||||
// MARK: - Check for completion.
|
||||
|
||||
if(phase_ == Phase::ReadyToPost) {
|
||||
const auto result = std::make_pair(
|
||||
consumed_,
|
||||
Instruction(
|
||||
operation_,
|
||||
source_,
|
||||
destination_,
|
||||
lock_,
|
||||
segment_override_,
|
||||
repetition_,
|
||||
Size(operation_size_),
|
||||
displacement_,
|
||||
operand_)
|
||||
);
|
||||
reset_parsing();
|
||||
return result;
|
||||
}
|
||||
|
||||
// i.e. not done yet.
|
||||
return std::make_pair(0, Instruction());
|
||||
}
|
||||
156
InstructionSets/x86/Decoder.hpp
Normal file
156
InstructionSets/x86/Decoder.hpp
Normal file
@ -0,0 +1,156 @@
|
||||
//
|
||||
// Decoder.hpp
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 1/1/21.
|
||||
// Copyright © 2021 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#ifndef InstructionSets_x86_Decoder_hpp
|
||||
#define InstructionSets_x86_Decoder_hpp
|
||||
|
||||
#include "Instruction.hpp"
|
||||
|
||||
#include <utility>
|
||||
|
||||
namespace CPU {
|
||||
namespace Decoder {
|
||||
namespace x86 {
|
||||
|
||||
enum class Model {
|
||||
i8086,
|
||||
};
|
||||
|
||||
/*!
|
||||
Implements Intel x86 instruction decoding.
|
||||
|
||||
This is an experimental implementation; it has not yet undergone significant testing.
|
||||
*/
|
||||
struct Decoder {
|
||||
public:
|
||||
Decoder(Model model);
|
||||
|
||||
/*!
|
||||
@returns an @c Instruction plus a size; a positive size to indicate successful decoding; a
|
||||
negative size specifies the [negatived] number of further bytes the caller should ideally
|
||||
collect before calling again. The caller is free to call with fewer, but may not get a decoded
|
||||
instruction in response, and the decoder may still not be able to complete decoding
|
||||
even if given that number of bytes.
|
||||
*/
|
||||
std::pair<int, Instruction> decode(const uint8_t *source, size_t length);
|
||||
|
||||
private:
|
||||
enum class Phase {
|
||||
/// Captures all prefixes and continues until an instruction byte is encountered.
|
||||
Instruction,
|
||||
/// Receives a ModRegRM byte and either populates the source_ and dest_ fields appropriately
|
||||
/// or completes decoding of the instruction, as per the instruction format.
|
||||
ModRegRM,
|
||||
/// Waits for sufficiently many bytes to pass for the required displacement and operand to be captured.
|
||||
/// Cf. displacement_size_ and operand_size_.
|
||||
AwaitingDisplacementOrOperand,
|
||||
/// Forms and returns an Instruction, and resets parsing state.
|
||||
ReadyToPost
|
||||
} phase_ = Phase::Instruction;
|
||||
|
||||
/// During the ModRegRM phase, format dictates interpretation of the ModRegRM byte.
|
||||
///
|
||||
/// During the ReadyToPost phase, format determines how transiently-recorded fields
|
||||
/// are packaged into an Instruction.
|
||||
enum class ModRegRMFormat: uint8_t {
|
||||
// Parse the ModRegRM for mode, register and register/memory fields
|
||||
// and populate the source_ and destination_ fields appropriate.
|
||||
MemReg_Reg,
|
||||
Reg_MemReg,
|
||||
|
||||
// Parse for mode and register/memory fields, populating both
|
||||
// source_ and destination_ fields with the result. Use the 'register'
|
||||
// field to pick an operation from the TEST/NOT/NEG/MUL/IMUL/DIV/IDIV group.
|
||||
MemRegTEST_to_IDIV,
|
||||
|
||||
// Parse for mode and register/memory fields, populating both
|
||||
// source_ and destination_ fields with the result. Use the 'register'
|
||||
// field to check for the POP operation.
|
||||
MemRegPOP,
|
||||
|
||||
// Parse for mode and register/memory fields, populating both
|
||||
// the destination_ field with the result and setting source_ to Immediate.
|
||||
// Use the 'register' field to check for the MOV operation.
|
||||
MemRegMOV,
|
||||
|
||||
// Parse for mode and register/memory fields, populating the
|
||||
// destination_ field with the result. Use the 'register' field
|
||||
// to pick an operation from the ROL/ROR/RCL/RCR/SAL/SHR/SAR group.
|
||||
MemRegROL_to_SAR,
|
||||
|
||||
// Parse for mode and register/memory fields, populating the
|
||||
// destination_ field with the result. Use the 'register' field
|
||||
// to pick an operation from the ADD/OR/ADC/SBB/AND/SUB/XOR/CMP group and
|
||||
// waits for an operand equal to the operation size.
|
||||
MemRegADD_to_CMP,
|
||||
|
||||
// Parse for mode and register/memory fields, populating the
|
||||
// source_ field with the result. Fills destination_ with a segment
|
||||
// register based on the reg field.
|
||||
SegReg,
|
||||
|
||||
// Parse for mode and register/memory fields, populating the
|
||||
// source_ and destination_ fields with the result. Uses the
|
||||
// 'register' field to pick INC or DEC.
|
||||
MemRegINC_DEC,
|
||||
|
||||
// Parse for mode and register/memory fields, populating the
|
||||
// source_ and destination_ fields with the result. Uses the
|
||||
// 'register' field to pick from INC/DEC/CALL/JMP/PUSH, altering
|
||||
// the source to ::Immediate and setting an operand size if necessary.
|
||||
MemRegINC_to_PUSH,
|
||||
|
||||
// Parse for mode and register/memory fields, populating the
|
||||
// source_ and destination_ fields with the result. Uses the
|
||||
// 'register' field to pick from ADD/ADC/SBB/SUB/CMP, altering
|
||||
// the source to ::Immediate and setting an appropriate operand size.
|
||||
MemRegADC_to_CMP,
|
||||
} modregrm_format_ = ModRegRMFormat::MemReg_Reg;
|
||||
|
||||
// Ephemeral decoding state.
|
||||
Operation operation_ = Operation::Invalid;
|
||||
uint8_t instr_ = 0x00; // TODO: is this desired, versus loading more context into ModRegRMFormat?
|
||||
int consumed_ = 0, operand_bytes_ = 0;
|
||||
|
||||
// Source and destination locations.
|
||||
Source source_ = Source::None;
|
||||
Source destination_ = Source::None;
|
||||
|
||||
// Immediate fields.
|
||||
int16_t displacement_ = 0;
|
||||
uint16_t operand_ = 0;
|
||||
uint64_t inward_data_ = 0;
|
||||
|
||||
// Facts about the instruction.
|
||||
int displacement_size_ = 0; // i.e. size of in-stream displacement, if any.
|
||||
int operand_size_ = 0; // i.e. size of in-stream operand, if any.
|
||||
int operation_size_ = 0; // i.e. size of data manipulated by the operation.
|
||||
|
||||
// Prefix capture fields.
|
||||
Repetition repetition_ = Repetition::None;
|
||||
bool lock_ = false;
|
||||
Source segment_override_ = Source::None;
|
||||
|
||||
/// Resets size capture and all fields with default values.
|
||||
void reset_parsing() {
|
||||
consumed_ = operand_bytes_ = 0;
|
||||
displacement_size_ = operand_size_ = 0;
|
||||
displacement_ = operand_ = 0;
|
||||
lock_ = false;
|
||||
segment_override_ = Source::None;
|
||||
repetition_ = Repetition::None;
|
||||
phase_ = Phase::Instruction;
|
||||
source_ = destination_ = Source::None;
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* InstructionSets_x86_Decoder_hpp */
|
||||
305
InstructionSets/x86/Instruction.hpp
Normal file
305
InstructionSets/x86/Instruction.hpp
Normal file
@ -0,0 +1,305 @@
|
||||
//
|
||||
// Instruction.hpp
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 1/15/21.
|
||||
// Copyright © 2021 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#ifndef InstructionSets_x86_Instruction_h
|
||||
#define InstructionSets_x86_Instruction_h
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
namespace CPU {
|
||||
namespace Decoder {
|
||||
namespace x86 {
|
||||
|
||||
/*
|
||||
Operations are documented below to establish expectations as to which
|
||||
instruction fields will be meaningful for each; this is a work-in-progress
|
||||
and may currently contain errors in the opcode descriptions — especially
|
||||
where implicit register dependencies are afoot.
|
||||
*/
|
||||
enum class Operation: uint8_t {
|
||||
Invalid,
|
||||
|
||||
/// ASCII adjust after addition; source will be AL and destination will be AX.
|
||||
AAA,
|
||||
/// ASCII adjust before division; destination will be AX and source will be a multiplier.
|
||||
AAD,
|
||||
/// ASCII adjust after multiplication; destination will be AX and source will be a divider.
|
||||
AAM,
|
||||
/// ASCII adjust after subtraction; source will be AL and destination will be AX.
|
||||
AAS,
|
||||
/// Decimal adjust after addition; source and destination will be AL.
|
||||
DAA,
|
||||
/// Decimal adjust after subtraction; source and destination will be AL.
|
||||
DAS,
|
||||
|
||||
/// Convert byte into word; source will be AL, destination will be AH.
|
||||
CBW,
|
||||
/// Convert word to double word; source will be AX and destination will be DX.
|
||||
CWD,
|
||||
|
||||
/// Escape, for a coprocessor; perform the bus cycles necessary to read the source and destination and perform a NOP.
|
||||
ESC,
|
||||
|
||||
/// Stops the processor until the next interrupt is fired.
|
||||
HLT,
|
||||
/// Waits until the WAIT input is asserted; if an interrupt occurs then it is serviced but returns to the WAIT.
|
||||
WAIT,
|
||||
|
||||
/// Add with carry; source, destination, operand and displacement will be populated appropriately.
|
||||
ADC,
|
||||
/// Add; source, destination, operand and displacement will be populated appropriately.
|
||||
ADD,
|
||||
/// Subtract with borrow; source, destination, operand and displacement will be populated appropriately.
|
||||
SBB,
|
||||
/// Subtract; source, destination, operand and displacement will be populated appropriately.
|
||||
SUB,
|
||||
/// Unsigned multiply; multiplies the source value by AX or AL, storing the result in DX:AX or AX.
|
||||
MUL,
|
||||
/// Signed multiply; multiplies the source value by AX or AL, storing the result in DX:AX or AX.
|
||||
IMUL,
|
||||
/// Unsigned divide; divide the source value by AX or AL, storing the quotient in AL and the remainder in AH.
|
||||
DIV,
|
||||
/// Signed divide; divide the source value by AX or AL, storing the quotient in AL and the remainder in AH.
|
||||
IDIV,
|
||||
|
||||
/// Increment; source, destination, operand and displacement will be populated appropriately.
|
||||
INC,
|
||||
/// Decrement; source, destination, operand and displacement will be populated appropriately.
|
||||
DEC,
|
||||
|
||||
/// Reads from the port specified by source to the destination.
|
||||
IN,
|
||||
/// Writes from the port specified by destination from the source.
|
||||
OUT,
|
||||
|
||||
// Various jumps; see the displacement to calculate targets.
|
||||
JO, JNO, JB, JNB, JE, JNE, JBE, JNBE,
|
||||
JS, JNS, JP, JNP, JL, JNL, JLE, JNLE,
|
||||
|
||||
/// Far call; see the segment() and offset() fields.
|
||||
CALLF,
|
||||
/// Displacement call; followed by a 16-bit operand providing a call offset.
|
||||
CALLD,
|
||||
/// Near call.
|
||||
CALLN,
|
||||
/// Return from interrupt.
|
||||
IRET,
|
||||
/// Near return; if source is not ::None then it will be an ::Immediate indicating how many additional bytes to remove from the stack.
|
||||
RETF,
|
||||
/// Far return; if source is not ::None then it will be an ::Immediate indicating how many additional bytes to remove from the stack.
|
||||
RETN,
|
||||
/// Near jump; if an operand is not ::None then it gives an absolute destination; otherwise see the displacement.
|
||||
JMPN,
|
||||
/// Far jump to the indicated segment and offset.
|
||||
JMPF,
|
||||
/// Relative jump performed only if CX = 0; see the displacement.
|
||||
JPCX,
|
||||
/// Generates a software interrupt of the level stated in the operand.
|
||||
INT,
|
||||
/// Generates a software interrupt of level 3.
|
||||
INT3,
|
||||
/// Generates a software interrupt of level 4 if overflow is set.
|
||||
INTO,
|
||||
|
||||
/// Load status flags to AH.
|
||||
LAHF,
|
||||
/// Load status flags from AH.
|
||||
SAHF,
|
||||
/// Load a segment and offset from the source into DS and the destination.
|
||||
LDS,
|
||||
/// Load a segment and offset from the source into ES and the destination.
|
||||
LES,
|
||||
/// Computes the effective address of the source and loads it into the destination.
|
||||
LEA,
|
||||
|
||||
/// Compare [bytes or words, per operation size]; source and destination implied to be DS:[SI] and ES:[DI].
|
||||
CMPS,
|
||||
/// Load string; reads from DS:SI into AL or AX, subject to segment override.
|
||||
LODS,
|
||||
/// Move string; moves a byte or word from DS:SI to ES:DI. If a segment override is provided, it overrides the the source.
|
||||
MOVS,
|
||||
/// Scan string; reads a byte or word from DS:SI and compares it to AL or AX.
|
||||
SCAS,
|
||||
/// Store string; store AL or AX to ES:DI.
|
||||
STOS,
|
||||
|
||||
// Perform a possibly-conditional loop, decrementing CX. See the displacement.
|
||||
LOOP, LOOPE, LOOPNE,
|
||||
|
||||
/// Loads the destination with the source.
|
||||
MOV,
|
||||
/// Negatives; source and destination point to the same thing, to negative.
|
||||
NEG,
|
||||
/// Logical NOT; source and destination point to the same thing, to negative.
|
||||
NOT,
|
||||
/// Logical AND; source, destination, operand and displacement will be populated appropriately.
|
||||
AND,
|
||||
/// Logical OR of source onto destination.
|
||||
OR,
|
||||
/// Logical XOR of source onto destination.
|
||||
XOR,
|
||||
/// NOP; no further fields.
|
||||
NOP,
|
||||
/// POP from the stack to destination.
|
||||
POP,
|
||||
/// POP from the stack to the flags register.
|
||||
POPF,
|
||||
/// PUSH the source to the stack.
|
||||
PUSH,
|
||||
/// PUSH the flags register to the stack.
|
||||
PUSHF,
|
||||
/// Rotate the destination left through carry the number of bits indicated by source.
|
||||
RCL,
|
||||
/// Rotate the destination right through carry the number of bits indicated by source.
|
||||
RCR,
|
||||
/// Rotate the destination left the number of bits indicated by source.
|
||||
ROL,
|
||||
/// Rotate the destination right the number of bits indicated by source.
|
||||
ROR,
|
||||
/// Arithmetic shift left the destination by the number of bits indicated by source.
|
||||
SAL,
|
||||
/// Arithmetic shift right the destination by the number of bits indicated by source.
|
||||
SAR,
|
||||
/// Logical shift right the destination by the number of bits indicated by source.
|
||||
SHR,
|
||||
|
||||
/// Clear carry flag; no source or destination provided.
|
||||
CLC,
|
||||
/// Clear direction flag; no source or destination provided.
|
||||
CLD,
|
||||
/// Clear interrupt flag; no source or destination provided.
|
||||
CLI,
|
||||
/// Set carry flag.
|
||||
STC,
|
||||
/// Set decimal flag.
|
||||
STD,
|
||||
/// Set interrupt flag.
|
||||
STI,
|
||||
/// Complement carry flag; no source or destination provided.
|
||||
CMC,
|
||||
|
||||
/// Compare; source, destination, operand and displacement will be populated appropriately.
|
||||
CMP,
|
||||
/// Sets flags based on the result of a logical AND of source and destination.
|
||||
TEST,
|
||||
|
||||
/// Exchanges the contents of the source and destination.
|
||||
XCHG,
|
||||
|
||||
/// Load AL with DS:[AL+BX].
|
||||
XLAT,
|
||||
};
|
||||
|
||||
enum class Size: uint8_t {
|
||||
Implied = 0,
|
||||
Byte = 1,
|
||||
Word = 2,
|
||||
DWord = 4,
|
||||
};
|
||||
|
||||
enum class Source: uint8_t {
|
||||
None,
|
||||
CS, DS, ES, SS,
|
||||
|
||||
AL, AH, AX,
|
||||
BL, BH, BX,
|
||||
CL, CH, CX,
|
||||
DL, DH, DX,
|
||||
|
||||
SI, DI,
|
||||
BP, SP,
|
||||
|
||||
IndBXPlusSI,
|
||||
IndBXPlusDI,
|
||||
IndBPPlusSI,
|
||||
IndBPPlusDI,
|
||||
IndSI,
|
||||
IndDI,
|
||||
DirectAddress,
|
||||
IndBP,
|
||||
IndBX,
|
||||
|
||||
Immediate
|
||||
};
|
||||
|
||||
enum class Repetition: uint8_t {
|
||||
None, RepE, RepNE
|
||||
};
|
||||
|
||||
class Instruction {
|
||||
public:
|
||||
Operation operation = Operation::Invalid;
|
||||
|
||||
bool operator ==(const Instruction &rhs) const {
|
||||
return
|
||||
repetition_size_ == rhs.repetition_size_ &&
|
||||
sources_ == rhs.sources_ &&
|
||||
displacement_ == rhs.displacement_ &&
|
||||
operand_ == rhs.operand_;
|
||||
}
|
||||
|
||||
private:
|
||||
// b0, b1: a Repetition;
|
||||
// b2+: operation size.
|
||||
uint8_t repetition_size_ = 0;
|
||||
|
||||
// b0–b5: source;
|
||||
// b6–b11: destination;
|
||||
// b12–b14: segment override;
|
||||
// b15: lock.
|
||||
uint16_t sources_ = 0;
|
||||
|
||||
// Unpackable fields.
|
||||
int16_t displacement_ = 0;
|
||||
uint16_t operand_ = 0; // ... or used to store a segment for far operations.
|
||||
|
||||
public:
|
||||
Source source() const { return Source(sources_ & 0x3f); }
|
||||
Source destination() const { return Source((sources_ >> 6) & 0x3f); }
|
||||
bool lock() const { return sources_ & 0x8000; }
|
||||
Source segment_override() const { return Source((sources_ >> 12) & 7); }
|
||||
|
||||
Repetition repetition() const { return Repetition(repetition_size_ & 3); }
|
||||
Size operation_size() const { return Size(repetition_size_ >> 2); }
|
||||
|
||||
uint16_t segment() const { return uint16_t(operand_); }
|
||||
uint16_t offset() const { return uint16_t(displacement_); }
|
||||
|
||||
int16_t displacement() const { return displacement_; }
|
||||
uint16_t operand() const { return operand_; }
|
||||
|
||||
Instruction() noexcept {}
|
||||
Instruction(
|
||||
Operation operation,
|
||||
Source source,
|
||||
Source destination,
|
||||
bool lock,
|
||||
Source segment_override,
|
||||
Repetition repetition,
|
||||
Size operation_size,
|
||||
int16_t displacement,
|
||||
uint16_t operand) noexcept :
|
||||
operation(operation),
|
||||
repetition_size_(uint8_t((int(operation_size) << 2) | int(repetition))),
|
||||
sources_(uint16_t(
|
||||
int(source) |
|
||||
(int(destination) << 6) |
|
||||
(int(segment_override) << 12) |
|
||||
(int(lock) << 15)
|
||||
)),
|
||||
displacement_(displacement),
|
||||
operand_(operand) {}
|
||||
};
|
||||
|
||||
static_assert(sizeof(Instruction) <= 8);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* InstructionSets_x86_Instruction_h */
|
||||
@ -185,6 +185,7 @@
|
||||
4B3BA0D01D318B44005DD7A7 /* MOS6532Bridge.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B3BA0CB1D318B44005DD7A7 /* MOS6532Bridge.mm */; };
|
||||
4B3BA0D11D318B44005DD7A7 /* TestMachine6502.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B3BA0CD1D318B44005DD7A7 /* TestMachine6502.mm */; };
|
||||
4B3BF5B01F146265005B6C36 /* CSW.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B3BF5AE1F146264005B6C36 /* CSW.cpp */; };
|
||||
4B3F76B925A1635300178AEC /* PowerPCDecoderTests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B3F76B825A1635300178AEC /* PowerPCDecoderTests.mm */; };
|
||||
4B3FCC40201EC24200960631 /* MultiMachine.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B3FCC3F201EC24200960631 /* MultiMachine.cpp */; };
|
||||
4B3FE75E1F3CF68B00448EE4 /* CPM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B3FE75C1F3CF68B00448EE4 /* CPM.cpp */; };
|
||||
4B448E811F1C45A00009ABD6 /* TZX.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B448E7F1F1C45A00009ABD6 /* TZX.cpp */; };
|
||||
@ -919,11 +920,20 @@
|
||||
4BEBFB4E2002C4BF000708CC /* MSXDSK.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEBFB4B2002C4BF000708CC /* MSXDSK.cpp */; };
|
||||
4BEBFB512002DB30000708CC /* DiskROM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEBFB4F2002DB30000708CC /* DiskROM.cpp */; };
|
||||
4BEBFB522002DB30000708CC /* DiskROM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEBFB4F2002DB30000708CC /* DiskROM.cpp */; };
|
||||
4BEDA3BA25B25563000C2DBD /* Decoder.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEDA3B425B25563000C2DBD /* Decoder.cpp */; };
|
||||
4BEDA3BB25B25563000C2DBD /* Decoder.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEDA3B425B25563000C2DBD /* Decoder.cpp */; };
|
||||
4BEDA3BC25B25563000C2DBD /* Decoder.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEDA3B425B25563000C2DBD /* Decoder.cpp */; };
|
||||
4BEDA3BD25B25563000C2DBD /* README.md in Resources */ = {isa = PBXBuildFile; fileRef = 4BEDA3B625B25563000C2DBD /* README.md */; };
|
||||
4BEDA3BE25B25563000C2DBD /* README.md in Resources */ = {isa = PBXBuildFile; fileRef = 4BEDA3B625B25563000C2DBD /* README.md */; };
|
||||
4BEDA3BF25B25563000C2DBD /* Decoder.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEDA3B925B25563000C2DBD /* Decoder.cpp */; };
|
||||
4BEDA3C025B25563000C2DBD /* Decoder.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEDA3B925B25563000C2DBD /* Decoder.cpp */; };
|
||||
4BEDA3C125B25563000C2DBD /* Decoder.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEDA3B925B25563000C2DBD /* Decoder.cpp */; };
|
||||
4BEE0A6F1D72496600532C7B /* Cartridge.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEE0A6A1D72496600532C7B /* Cartridge.cpp */; };
|
||||
4BEE0A701D72496600532C7B /* PRG.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEE0A6D1D72496600532C7B /* PRG.cpp */; };
|
||||
4BEE149A227FC0EA00133682 /* IWM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BEE1498227FC0EA00133682 /* IWM.cpp */; };
|
||||
4BEE1EC022B5E236000A26A6 /* MacGCRTests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4BEE1EBF22B5E236000A26A6 /* MacGCRTests.mm */; };
|
||||
4BEE1EC122B5E2FD000A26A6 /* Encoder.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BD67DCE209BF27B00AB2146 /* Encoder.cpp */; };
|
||||
4BEE4BD425A26E2B00011BD2 /* x86DecoderTests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4BEE4BD325A26E2B00011BD2 /* x86DecoderTests.mm */; };
|
||||
4BEEE6BD20DC72EB003723BF /* CompositeOptions.xib in Resources */ = {isa = PBXBuildFile; fileRef = 4BEEE6BB20DC72EA003723BF /* CompositeOptions.xib */; };
|
||||
4BEF6AAA1D35CE9E00E73575 /* DigitalPhaseLockedLoopBridge.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4BEF6AA91D35CE9E00E73575 /* DigitalPhaseLockedLoopBridge.mm */; };
|
||||
4BEF6AAC1D35D1C400E73575 /* DPLLTests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 4BEF6AAB1D35D1C400E73575 /* DPLLTests.swift */; };
|
||||
@ -1138,6 +1148,7 @@
|
||||
4B3BA0CD1D318B44005DD7A7 /* TestMachine6502.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = TestMachine6502.mm; sourceTree = "<group>"; };
|
||||
4B3BF5AE1F146264005B6C36 /* CSW.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = CSW.cpp; sourceTree = "<group>"; };
|
||||
4B3BF5AF1F146264005B6C36 /* CSW.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = CSW.hpp; sourceTree = "<group>"; };
|
||||
4B3F76B825A1635300178AEC /* PowerPCDecoderTests.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = PowerPCDecoderTests.mm; sourceTree = "<group>"; };
|
||||
4B3FCC3E201EC24200960631 /* MultiMachine.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = MultiMachine.hpp; sourceTree = "<group>"; };
|
||||
4B3FCC3F201EC24200960631 /* MultiMachine.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = MultiMachine.cpp; sourceTree = "<group>"; };
|
||||
4B3FE75C1F3CF68B00448EE4 /* CPM.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = CPM.cpp; path = Parsers/CPM.cpp; sourceTree = "<group>"; };
|
||||
@ -1916,6 +1927,13 @@
|
||||
4BEBFB4C2002C4BF000708CC /* MSXDSK.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = MSXDSK.hpp; sourceTree = "<group>"; };
|
||||
4BEBFB4F2002DB30000708CC /* DiskROM.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; name = DiskROM.cpp; path = MSX/DiskROM.cpp; sourceTree = "<group>"; };
|
||||
4BEBFB502002DB30000708CC /* DiskROM.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; name = DiskROM.hpp; path = MSX/DiskROM.hpp; sourceTree = "<group>"; };
|
||||
4BEDA3B425B25563000C2DBD /* Decoder.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = Decoder.cpp; sourceTree = "<group>"; };
|
||||
4BEDA3B525B25563000C2DBD /* Decoder.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = Decoder.hpp; sourceTree = "<group>"; };
|
||||
4BEDA3B625B25563000C2DBD /* README.md */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = net.daringfireball.markdown; path = README.md; sourceTree = "<group>"; };
|
||||
4BEDA3B825B25563000C2DBD /* Decoder.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = Decoder.hpp; sourceTree = "<group>"; };
|
||||
4BEDA3B925B25563000C2DBD /* Decoder.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = Decoder.cpp; sourceTree = "<group>"; };
|
||||
4BEDA3D225B257F2000C2DBD /* Instruction.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Instruction.hpp; sourceTree = "<group>"; };
|
||||
4BEDA3DB25B2588F000C2DBD /* Instruction.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Instruction.hpp; sourceTree = "<group>"; };
|
||||
4BEE0A6A1D72496600532C7B /* Cartridge.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = Cartridge.cpp; sourceTree = "<group>"; };
|
||||
4BEE0A6B1D72496600532C7B /* Cartridge.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = Cartridge.hpp; sourceTree = "<group>"; };
|
||||
4BEE0A6D1D72496600532C7B /* PRG.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = PRG.cpp; sourceTree = "<group>"; };
|
||||
@ -1923,6 +1941,7 @@
|
||||
4BEE1498227FC0EA00133682 /* IWM.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = IWM.cpp; sourceTree = "<group>"; };
|
||||
4BEE1499227FC0EA00133682 /* IWM.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = IWM.hpp; sourceTree = "<group>"; };
|
||||
4BEE1EBF22B5E236000A26A6 /* MacGCRTests.mm */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.objcpp; path = MacGCRTests.mm; sourceTree = "<group>"; };
|
||||
4BEE4BD325A26E2B00011BD2 /* x86DecoderTests.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = x86DecoderTests.mm; sourceTree = "<group>"; };
|
||||
4BEEE6BC20DC72EA003723BF /* Base */ = {isa = PBXFileReference; lastKnownFileType = file.xib; name = Base; path = "Clock Signal/Base.lproj/CompositeOptions.xib"; sourceTree = SOURCE_ROOT; };
|
||||
4BEF6AA81D35CE9E00E73575 /* DigitalPhaseLockedLoopBridge.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = DigitalPhaseLockedLoopBridge.h; sourceTree = "<group>"; };
|
||||
4BEF6AA91D35CE9E00E73575 /* DigitalPhaseLockedLoopBridge.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = DigitalPhaseLockedLoopBridge.mm; sourceTree = "<group>"; };
|
||||
@ -3774,6 +3793,7 @@
|
||||
4B31B88E1FBFBCD800C140D5 /* Configurable */,
|
||||
4B055A761FAE78210060FFFF /* Frameworks */,
|
||||
4B86E2581F8C628F006FAA45 /* Inputs */,
|
||||
4BEDA3B225B25563000C2DBD /* InstructionSets */,
|
||||
4BB73EDC1B587CA500552FC2 /* Machines */,
|
||||
4B7BA03C23D55E7900B98D9E /* Numeric */,
|
||||
4B366DFD1B5C165F0026627B /* Outputs */,
|
||||
@ -3851,9 +3871,11 @@
|
||||
4BC0CB272446BC7B00A79DBB /* OPLTests.mm */,
|
||||
4B121F9A1E06293F00BFDA12 /* PCMSegmentEventSourceTests.mm */,
|
||||
4BD4A8CF1E077FD20020D856 /* PCMTrackTests.mm */,
|
||||
4B3F76B825A1635300178AEC /* PowerPCDecoderTests.mm */,
|
||||
4BE76CF822641ED300ACD6FA /* QLTests.mm */,
|
||||
4B2AF8681E513FC20027EE29 /* TIATests.mm */,
|
||||
4B1D08051E0F7A1100763741 /* TimeTests.mm */,
|
||||
4BEE4BD325A26E2B00011BD2 /* x86DecoderTests.mm */,
|
||||
4BB73EB81B587A5100552FC2 /* Info.plist */,
|
||||
4BC9E1ED1D23449A003FCEE4 /* 6502InterruptTests.swift */,
|
||||
4B92EAC91B7C112B00246143 /* 6502TimingTests.swift */,
|
||||
@ -4327,6 +4349,37 @@
|
||||
name = Zexall;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4BEDA3B225B25563000C2DBD /* InstructionSets */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4BEDA3B625B25563000C2DBD /* README.md */,
|
||||
4BEDA3B325B25563000C2DBD /* PowerPC */,
|
||||
4BEDA3B725B25563000C2DBD /* x86 */,
|
||||
);
|
||||
name = InstructionSets;
|
||||
path = ../../InstructionSets;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4BEDA3B325B25563000C2DBD /* PowerPC */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4BEDA3B425B25563000C2DBD /* Decoder.cpp */,
|
||||
4BEDA3B525B25563000C2DBD /* Decoder.hpp */,
|
||||
4BEDA3D225B257F2000C2DBD /* Instruction.hpp */,
|
||||
);
|
||||
path = PowerPC;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4BEDA3B725B25563000C2DBD /* x86 */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
4BEDA3B925B25563000C2DBD /* Decoder.cpp */,
|
||||
4BEDA3B825B25563000C2DBD /* Decoder.hpp */,
|
||||
4BEDA3DB25B2588F000C2DBD /* Instruction.hpp */,
|
||||
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|
||||
path = x86;
|
||||
sourceTree = "<group>";
|
||||
};
|
||||
4BEE0A691D72496600532C7B /* Cartridge */ = {
|
||||
isa = PBXGroup;
|
||||
children = (
|
||||
@ -4557,6 +4610,7 @@
|
||||
4B2C45421E3C3896002A2389 /* cartridge.png in Resources */,
|
||||
4BB73EA91B587A5100552FC2 /* Assets.xcassets in Resources */,
|
||||
4B79E4451E3AF38600141F11 /* floppy35.png in Resources */,
|
||||
4BEDA3BD25B25563000C2DBD /* README.md in Resources */,
|
||||
4B55DD8420DF06680043F2E5 /* MachinePicker.xib in Resources */,
|
||||
4BDA00DA22E60EE300AC3CD0 /* ROMRequester.xib in Resources */,
|
||||
4BC5FC3020CDDDEF00410AA0 /* AppleIIOptions.xib in Resources */,
|
||||
@ -4593,6 +4647,7 @@
|
||||
4BB2994E1B587D8400A49093 /* dexn in Resources */,
|
||||
4BB299971B587D8400A49093 /* nopa in Resources */,
|
||||
4B018B89211930DE002A3937 /* 65C02_extended_opcodes_test.bin in Resources */,
|
||||
4BEDA3BE25B25563000C2DBD /* README.md in Resources */,
|
||||
4BFCA1291ECBE7A700AC40C1 /* zexall.com in Resources */,
|
||||
4BB299521B587D8400A49093 /* eoray in Resources */,
|
||||
4BB299411B587D8400A49093 /* cpyb in Resources */,
|
||||
@ -5080,6 +5135,7 @@
|
||||
4BE2121A253FCE9C00435408 /* AppleIIgs.cpp in Sources */,
|
||||
4B89451F201967B4007DE474 /* Tape.cpp in Sources */,
|
||||
4B055AA81FAE85EF0060FFFF /* Shifter.cpp in Sources */,
|
||||
4BEDA3BC25B25563000C2DBD /* Decoder.cpp in Sources */,
|
||||
4B8318B422D3E546006DB630 /* DriveSpeedAccumulator.cpp in Sources */,
|
||||
4B055AC81FAE9AFB0060FFFF /* C1540.cpp in Sources */,
|
||||
4B055A8F1FAE85A90060FFFF /* FileHolder.cpp in Sources */,
|
||||
@ -5114,6 +5170,7 @@
|
||||
4B0F94FF208C1A1600FE41D9 /* NIB.cpp in Sources */,
|
||||
4B0E04EB1FC9E78800F43484 /* CAS.cpp in Sources */,
|
||||
4BB0A65D2045009000FB3688 /* ColecoVision.cpp in Sources */,
|
||||
4BEDA3C125B25563000C2DBD /* Decoder.cpp in Sources */,
|
||||
4BB0A65C2044FD3000FB3688 /* SN76489.cpp in Sources */,
|
||||
4B595FAE2086DFBA0083CAA8 /* AudioToggle.cpp in Sources */,
|
||||
4B055AB91FAE86170060FFFF /* Acorn.cpp in Sources */,
|
||||
@ -5189,6 +5246,7 @@
|
||||
4B54C0BF1F8D8F450050900F /* Keyboard.cpp in Sources */,
|
||||
4B3FE75E1F3CF68B00448EE4 /* CPM.cpp in Sources */,
|
||||
4B2BFDB21DAEF5FF001A68B8 /* Video.cpp in Sources */,
|
||||
4BEDA3BF25B25563000C2DBD /* Decoder.cpp in Sources */,
|
||||
4B4DC82B1D2C27A4003C5BF8 /* SerialBus.cpp in Sources */,
|
||||
4BBFFEE61F7B27F1005F3FEB /* TrackSerialiser.cpp in Sources */,
|
||||
4BAE49582032881E004BE78E /* CSZX8081.mm in Sources */,
|
||||
@ -5228,6 +5286,7 @@
|
||||
4B45189F1F75FD1C00926311 /* AcornADF.cpp in Sources */,
|
||||
4B7BA03023C2B19C00B98D9E /* Jasmin.cpp in Sources */,
|
||||
4B7136911F789C93008B8ED9 /* SegmentParser.cpp in Sources */,
|
||||
4BEDA3BA25B25563000C2DBD /* Decoder.cpp in Sources */,
|
||||
4B4518A21F75FD1C00926311 /* G64.cpp in Sources */,
|
||||
4B89452C201967B4007DE474 /* Tape.cpp in Sources */,
|
||||
4B448E811F1C45A00009ABD6 /* TZX.cpp in Sources */,
|
||||
@ -5357,6 +5416,7 @@
|
||||
4B778F4223A5F1A70000D260 /* MemoryFuzzer.cpp in Sources */,
|
||||
4B778F0123A5EBA00000D260 /* MacintoshIMG.cpp in Sources */,
|
||||
4BFF1D3D2235C3C100838EA1 /* EmuTOSTests.mm in Sources */,
|
||||
4B3F76B925A1635300178AEC /* PowerPCDecoderTests.mm in Sources */,
|
||||
4B778F0A23A5EC150000D260 /* TapePRG.cpp in Sources */,
|
||||
4B778F0823A5EC150000D260 /* CSW.cpp in Sources */,
|
||||
4B778F5323A5F23F0000D260 /* SerialBus.cpp in Sources */,
|
||||
@ -5414,6 +5474,7 @@
|
||||
4B778F4823A5F1E70000D260 /* StaticAnalyser.cpp in Sources */,
|
||||
4B92EACA1B7C112B00246143 /* 6502TimingTests.swift in Sources */,
|
||||
4B778F2823A5EEF80000D260 /* Cartridge.cpp in Sources */,
|
||||
4BEDA3C025B25563000C2DBD /* Decoder.cpp in Sources */,
|
||||
4B778F4C23A5F2090000D260 /* StaticAnalyser.cpp in Sources */,
|
||||
4B778F2623A5EE350000D260 /* Acorn.cpp in Sources */,
|
||||
4B778F5B23A5F2DE0000D260 /* Tape.cpp in Sources */,
|
||||
@ -5424,6 +5485,7 @@
|
||||
4BEE1EC122B5E2FD000A26A6 /* Encoder.cpp in Sources */,
|
||||
4B121F9B1E06293F00BFDA12 /* PCMSegmentEventSourceTests.mm in Sources */,
|
||||
4B778EFF23A5EB940000D260 /* D64.cpp in Sources */,
|
||||
4BEDA3BB25B25563000C2DBD /* Decoder.cpp in Sources */,
|
||||
4B778F2423A5EDEE0000D260 /* PRG.cpp in Sources */,
|
||||
4B778F5A23A5F2D50000D260 /* 6502.cpp in Sources */,
|
||||
4B778F6223A5F35F0000D260 /* File.cpp in Sources */,
|
||||
@ -5483,6 +5545,7 @@
|
||||
4B778F2123A5EDD50000D260 /* TrackSerialiser.cpp in Sources */,
|
||||
4B049CDD1DA3C82F00322067 /* BCDTest.swift in Sources */,
|
||||
4B778F3923A5F11C0000D260 /* Shifter.cpp in Sources */,
|
||||
4BEE4BD425A26E2B00011BD2 /* x86DecoderTests.mm in Sources */,
|
||||
4B778F3623A5F1040000D260 /* Target.cpp in Sources */,
|
||||
4B1D08061E0F7A1100763741 /* TimeTests.mm in Sources */,
|
||||
4B778F3D23A5F1750000D260 /* ncr5380.cpp in Sources */,
|
||||
|
||||
390
OSBindings/Mac/Clock SignalTests/PowerPCDecoderTests.mm
Normal file
390
OSBindings/Mac/Clock SignalTests/PowerPCDecoderTests.mm
Normal file
@ -0,0 +1,390 @@
|
||||
//
|
||||
// PowerPCDecoderTests.m
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 02/01/2021.
|
||||
// Copyright 2021 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#import <XCTest/XCTest.h>
|
||||
|
||||
#include "../../../InstructionSets/PowerPC/Decoder.hpp"
|
||||
|
||||
namespace {
|
||||
using Operation = CPU::Decoder::PowerPC::Operation;
|
||||
using Instruction = CPU::Decoder::PowerPC::Instruction;
|
||||
}
|
||||
|
||||
@interface PowerPCDecoderTests : XCTestCase
|
||||
@end
|
||||
|
||||
/*!
|
||||
Tests PowerPC decoding by throwing a bunch of randomly-generated
|
||||
word streams and checking that the result matches what I got from a
|
||||
disassembler elsewhere.
|
||||
*/
|
||||
@implementation PowerPCDecoderTests {
|
||||
Instruction instructions[32];
|
||||
}
|
||||
|
||||
// MARK: - Specific instruction asserts.
|
||||
|
||||
- (void)assertUndefined:(Instruction &)instruction {
|
||||
XCTAssertEqual(instruction.operation, Operation::Undefined);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation rD:(int)rD rA:(int)rA simm:(int)simm {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.rD(), rD);
|
||||
XCTAssertEqual(instruction.rA(), rA);
|
||||
XCTAssertEqual(instruction.simm(), simm);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation rD:(int)rD rA:(int)rA d:(int)d {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.rD(), rD);
|
||||
XCTAssertEqual(instruction.rA(), rA);
|
||||
XCTAssertEqual(instruction.d(), d);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation rA:(int)rA rS:(int)rS uimm:(int)uimm {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.rA(), rA);
|
||||
XCTAssertEqual(instruction.rS(), rS);
|
||||
XCTAssertEqual(instruction.uimm(), uimm);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation rS:(int)rS rA:(int)rA d:(int)d {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.rS(), rS);
|
||||
XCTAssertEqual(instruction.rA(), rA);
|
||||
XCTAssertEqual(instruction.d(), d);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation frD:(int)frD rA:(int)rA d:(int)d {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.frD(), frD);
|
||||
XCTAssertEqual(instruction.rA(), rA);
|
||||
XCTAssertEqual(instruction.d(), d);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation frS:(int)frS rA:(int)rA d:(int)d {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.frS(), frS);
|
||||
XCTAssertEqual(instruction.rA(), rA);
|
||||
XCTAssertEqual(instruction.d(), d);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation li:(uint32_t)li lk:(BOOL)lk aa:(BOOL)aa {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.li(), li);
|
||||
XCTAssertEqual(!!instruction.lk(), lk);
|
||||
XCTAssertEqual(!!instruction.aa(), aa);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation bo:(int)bo bi:(int)bi bd:(int)bd lk:(BOOL)lk aa:(BOOL)aa {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.bo(), bo);
|
||||
XCTAssertEqual(instruction.bi(), bi);
|
||||
XCTAssertEqual(instruction.bd(), bd);
|
||||
XCTAssertEqual(!!instruction.lk(), lk);
|
||||
XCTAssertEqual(!!instruction.aa(), aa);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation rA:(int)rA rS:(int)rS rB:(int)rB mb:(int)mb me:(int)me rc:(BOOL)rc {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.rA(), rA);
|
||||
XCTAssertEqual(instruction.rS(), rS);
|
||||
XCTAssertEqual(instruction.rB(), rB);
|
||||
XCTAssertEqual(instruction.mb(), mb);
|
||||
XCTAssertEqual(instruction.me(), me);
|
||||
XCTAssertEqual(!!instruction.rc(), rc);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation to:(int)to rA:(int)rA simm:(int)simm {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.to(), to);
|
||||
XCTAssertEqual(instruction.rA(), rA);
|
||||
XCTAssertEqual(instruction.simm(), simm);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation crfD:(int)crfD l:(BOOL)l rA:(int)rA uimm:(int)uimm {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.crfD(), crfD);
|
||||
XCTAssertEqual(!!instruction.l(), l);
|
||||
XCTAssertEqual(instruction.rA(), rA);
|
||||
XCTAssertEqual(instruction.uimm(), uimm);
|
||||
}
|
||||
|
||||
// MARK: - Decoder
|
||||
|
||||
- (void)decode:(const uint32_t *)stream {
|
||||
CPU::Decoder::PowerPC::Decoder decoder(CPU::Decoder::PowerPC::Model::MPC601);
|
||||
for(int c = 0; c < 32; c++) {
|
||||
instructions[c] = decoder.decode(stream[c]);
|
||||
}
|
||||
}
|
||||
|
||||
// MARK: - Tests
|
||||
|
||||
- (void)testSequence1 {
|
||||
const uint32_t sequence[] = {
|
||||
0x32eeefa5, 0xc2ee0786, 0x80ce552c, 0x88d5f02a,
|
||||
0xf8c2e801, 0xe83d5cdf, 0x7fa51fbb, 0xaacea8b0,
|
||||
0x7d4d4d21, 0x1314cf89, 0x47e0014b, 0xdf67566d,
|
||||
0xfb29a33e, 0x312cbf53, 0x706f1a15, 0xa87b7011,
|
||||
0x2107090c, 0xce04935e, 0x642e464a, 0x931e8eba,
|
||||
0xee396d5b, 0x4901183d, 0x31ccaa9a, 0x42b61a86,
|
||||
0x1ed4751d, 0x86af76e4, 0x151405a9, 0xca0ac015,
|
||||
0x60dd1f9d, 0xecff44f6, 0xf2c1110e, 0x9aa6653b,
|
||||
};
|
||||
[self decode:sequence];
|
||||
|
||||
// addic r23,r14,-4187
|
||||
// lfs f23,1926(r14)
|
||||
// lwz r6,21804(r14)
|
||||
// lbz r6,-4054(r21)
|
||||
[self assert:instructions[0] operation:Operation::addic rD:23 rA:14 simm:-4187];
|
||||
[self assert:instructions[1] operation:Operation::lfs frD:23 rA:14 d:1926];
|
||||
[self assert:instructions[2] operation:Operation::lwz rD:6 rA:14 d:21804];
|
||||
[self assert:instructions[3] operation:Operation::lbz rD:6 rA:21 d:-4054];
|
||||
|
||||
// .long 0xf8c2e801
|
||||
// .long 0xe83d5cdf
|
||||
// .long 0x7fa51fbb
|
||||
// lha r22,-22352(r14)
|
||||
[self assertUndefined:instructions[4]];
|
||||
[self assertUndefined:instructions[5]];
|
||||
[self assertUndefined:instructions[6]];
|
||||
[self assert:instructions[7] operation:Operation::lha rD:22 rA:14 d:-22352];
|
||||
|
||||
// .long 0x7d4d4d21
|
||||
// .long 0x1314cf89
|
||||
// .long 0x47e0014b
|
||||
[self assertUndefined:instructions[8]];
|
||||
[self assertUndefined:instructions[9]];
|
||||
// CLK decodes this as sc because it ignores reserved bits; the disassembler
|
||||
// I used checks the reserved bits. For now: don't test.
|
||||
// XCTAssertEqual(instructions[10].operation, Operation::Undefined);
|
||||
|
||||
// stfdu f27,22125(r7)
|
||||
// .long 0xfb29a33e
|
||||
// addic r9,r12,-16557
|
||||
// andi. r15,r3,6677
|
||||
[self assert:instructions[11] operation:Operation::stfdu frS:27 rA:7 d:22125];
|
||||
[self assertUndefined:instructions[12]];
|
||||
[self assert:instructions[13] operation:Operation::addic rD:9 rA:12 simm:-16557];
|
||||
[self assert:instructions[14] operation:Operation::andi_ rA:15 rS:3 uimm:6677];
|
||||
|
||||
// lha r3,28689(r27)
|
||||
// subfic r8,r7,2316
|
||||
// lfdu f16,-27810(r4)
|
||||
// oris r14,r1,17994
|
||||
[self assert:instructions[15] operation:Operation::lha rD:3 rA:27 d:28689];
|
||||
[self assert:instructions[16] operation:Operation::subfic rD:8 rA:7 simm:2316];
|
||||
[self assert:instructions[17] operation:Operation::lfdu frD:16 rA:4 d:-27810];
|
||||
[self assert:instructions[18] operation:Operation::oris rA:14 rS:1 uimm:17994];
|
||||
|
||||
// stw r24,-28998(r30)
|
||||
// .long 0xee396d5b
|
||||
// bl 0x01011890 [disassmebled at address 0x54]
|
||||
// addic r14,r12,-21862
|
||||
[self assert:instructions[19] operation:Operation::stw rS:24 rA:30 d:-28998];
|
||||
[self assertUndefined:instructions[20]];
|
||||
[self assert:instructions[21] operation:Operation::bx li:0x01011890 - 0x54 lk:TRUE aa:FALSE];
|
||||
[self assert:instructions[22] operation:Operation::addic rD:14 rA:12 simm:-21862];
|
||||
|
||||
// .long 0x42b61a86 [10101]
|
||||
// mulli r22,r20,29981
|
||||
// lwzu r21,30436(r15)
|
||||
// .long 0x151405a9
|
||||
[self assertUndefined:instructions[23]];
|
||||
[self assert:instructions[24] operation:Operation::mulli rD:22 rA:20 simm:29981];
|
||||
[self assert:instructions[25] operation:Operation::lwzu rD:21 rA:15 d:30436];
|
||||
[self assertUndefined:instructions[26]];
|
||||
|
||||
// lfd f16,-16363(r10)
|
||||
// ori r29,r6,8093
|
||||
// .long 0xecff44f6
|
||||
// .long 0xf2c1110e
|
||||
// stb r21,25915(r6)
|
||||
[self assert:instructions[27] operation:Operation::lfd frD:16 rA:10 d:-16363];
|
||||
[self assert:instructions[28] operation:Operation::ori rA:29 rS:6 uimm:8093];
|
||||
[self assertUndefined:instructions[29]];
|
||||
[self assertUndefined:instructions[30]];
|
||||
[self assert:instructions[31] operation:Operation::stb rS:21 rA:6 d:25915];
|
||||
}
|
||||
|
||||
- (void)testSequence2 {
|
||||
const uint32_t sequence[] = {
|
||||
0x90252dae, 0x7429ee14, 0x618935bc, 0xd6c94af0,
|
||||
0xba1d295f, 0x649e3869, 0x6def742c, 0x5c64cdce,
|
||||
0x762d59ee, 0x565c8189, 0xc7c59f81, 0xce1157fd,
|
||||
0xc86aef59, 0x81325882, 0x1336fad6, 0xe1ddfa2b,
|
||||
0x18c60357, 0x4c122cb5, 0xccb1f749, 0xdbdcebc3,
|
||||
0x0fc60187, 0x117eb911, 0x80334c43, 0xe65371e8,
|
||||
0xa047c94d, 0xe671dd0b, 0xe07992bb, 0x6a332fe8,
|
||||
0xfc361c6b, 0x5e8b5a28, 0xb2b64a22, 0x045dd156,
|
||||
};
|
||||
[self decode:sequence];
|
||||
|
||||
// stw r1,11694(r5)
|
||||
// andis. r9,r1,60948
|
||||
// ori r9,r12,13756
|
||||
// stfsu f22,19184(r9)
|
||||
[self assert:instructions[0] operation:Operation::stw rS:1 rA:5 d:11694];
|
||||
[self assert:instructions[1] operation:Operation::andis_ rA:9 rS:1 uimm:60948];
|
||||
[self assert:instructions[2] operation:Operation::ori rA:9 rS:12 uimm:13756];
|
||||
[self assert:instructions[3] operation:Operation::stfsu frS:22 rA:9 d:19184];
|
||||
|
||||
// lmw r16,10591(r29)
|
||||
// oris r30,r4,14441
|
||||
// xoris r15,r15,29740
|
||||
// rlwnm r4,r3,r25,23,7
|
||||
[self assert:instructions[4] operation:Operation::lmw rD:16 rA:29 d:10591];
|
||||
[self assert:instructions[5] operation:Operation::oris rA:30 rS:4 uimm:14441];
|
||||
[self assert:instructions[6] operation:Operation::xoris rA:15 rS:15 uimm:29740];
|
||||
[self assert:instructions[7] operation:Operation::rlwnmx rA:4 rS:3 rB:25 mb:23 me:7 rc:FALSE];
|
||||
|
||||
// andis. r13,r17,23022
|
||||
// rlwinm. r28,r18,16,6,4
|
||||
// lfsu f30,-24703(r5)
|
||||
// lfdu f16,22525(r17)
|
||||
[self assert:instructions[8] operation:Operation::andis_ rA:13 rS:17 uimm:23022];
|
||||
[self assert:instructions[9] operation:Operation::rlwinmx rA:28 rS:18 rB:16 mb:6 me:4 rc:TRUE];
|
||||
[self assert:instructions[10] operation:Operation::lfsu frD:30 rA:5 d:-24703];
|
||||
[self assert:instructions[11] operation:Operation::lfdu frD:16 rA:17 d:22525];
|
||||
|
||||
// lfd f3,-4263(r10)
|
||||
// lwz r9,22658(r18)
|
||||
// .long 0x1336fad6
|
||||
// .long 0xe1ddfa2b
|
||||
[self assert:instructions[12] operation:Operation::lfd frD:3 rA:10 d:-4263];
|
||||
[self assert:instructions[13] operation:Operation::lwz rD:9 rA:18 d:22658];
|
||||
[self assertUndefined:instructions[14]];
|
||||
[self assertUndefined:instructions[15]];
|
||||
|
||||
// .long 0x18c60357
|
||||
// .long 0x4c122cb5
|
||||
// lfdu f5,-2231(r17)
|
||||
// stfd f30,-5181(r28)
|
||||
[self assertUndefined:instructions[16]];
|
||||
[self assertUndefined:instructions[17]];
|
||||
[self assert:instructions[18] operation:Operation::lfdu frD:5 rA:17 d:-2231];
|
||||
[self assert:instructions[19] operation:Operation::stfd frD:30 rA:28 d:-5181];
|
||||
|
||||
// twi 30,r6,391
|
||||
// .long 0x117eb911
|
||||
// lwz r1,19523(r19)
|
||||
// .long 0xe65371e8
|
||||
[self assert:instructions[20] operation:Operation::twi to:30 rA:6 simm:391];
|
||||
[self assertUndefined:instructions[21]];
|
||||
[self assert:instructions[22] operation:Operation::lwz rD:1 rA:19 d:19523];
|
||||
[self assertUndefined:instructions[23]];
|
||||
|
||||
// lhz r2,-14003(r7)
|
||||
// .long 0xe671dd0b
|
||||
// .long 0xe07992bb
|
||||
// xori r19,r17,12264
|
||||
[self assert:instructions[24] operation:Operation::lhz rD:2 rA:7 d:-14003];
|
||||
[self assertUndefined:instructions[25]];
|
||||
[self assertUndefined:instructions[26]];
|
||||
[self assert:instructions[27] operation:Operation::xori rA:19 rS:17 uimm:12264];
|
||||
|
||||
// .long 0xfc361c6b
|
||||
// rlwnm r11,r20,r11,8,20
|
||||
// sth r21,18978(r22)
|
||||
// .long 0x45dd156
|
||||
// [self assertUndefined:instructions[28]]; // Disabled due to reserved field; I'm decoding this as faddx.
|
||||
[self assert:instructions[29] operation:Operation::rlwnmx rA:11 rS:20 rB:11 mb:8 me:20 rc:FALSE];
|
||||
[self assert:instructions[30] operation:Operation::sth rS:21 rA:22 d:18978];
|
||||
[self assertUndefined:instructions[31]];
|
||||
}
|
||||
|
||||
- (void)testSequence3 {
|
||||
const uint32_t sequence[] = {
|
||||
0xbcaf3520, 0xfa9df12d, 0xc631efca, 0xa3e7f409,
|
||||
0x3ddca273, 0x3cfb234d, 0x551dc325, 0x8c1a0f37,
|
||||
0x5b3ca99b, 0xce08cc1e, 0x7b1dfd3a, 0xf19aee7c,
|
||||
0x52c852e9, 0xc681c0c1, 0xd3b1fda5, 0xe2b401cb,
|
||||
0x433cb83d, 0x54412f41, 0x532d624a, 0x0b3117c5,
|
||||
0x988144ba, 0xc7a96ad0, 0x28331474, 0x5620c367,
|
||||
0xab0a2607, 0xe826acf4, 0x41969154, 0x6471d09f,
|
||||
0x6a25f04f, 0x4a15996d, 0x272c96ef, 0xab3171a9,
|
||||
};
|
||||
[self decode:sequence];
|
||||
|
||||
// stmw r5,13600(r15)
|
||||
// .long 0xfa9df12d
|
||||
// lfsu f17,-4150(r17)
|
||||
// lhz r31,-3063(r7)
|
||||
[self assert:instructions[0] operation:Operation::stmw rS:5 rA:15 d:13600];
|
||||
[self assertUndefined:instructions[1]];
|
||||
[self assert:instructions[2] operation:Operation::lfsu frD:17 rA:17 d:-4150];
|
||||
[self assert:instructions[3] operation:Operation::lhz rD:31 rA:7 d:-3063];
|
||||
|
||||
// addis r14,r28,-23949
|
||||
// addis r7,r27,9037
|
||||
// rlwinm. r29,r8,24,12,18
|
||||
// lbzu r0,3895(r26)
|
||||
[self assert:instructions[4] operation:Operation::addis rD:14 rA:28 simm:-23949];
|
||||
[self assert:instructions[5] operation:Operation::addis rD:7 rA:27 simm:9037];
|
||||
[self assert:instructions[6] operation:Operation::rlwinmx rA:29 rS:8 rB:24 mb:12 me:18 rc:TRUE];
|
||||
[self assert:instructions[7] operation:Operation::lbzu rD:0 rA:26 d:3895];
|
||||
|
||||
// rlmi. r28,r25,r21,6,13
|
||||
// lfdu f16,-13282(r8)
|
||||
// .long 0x7b1dfd3a
|
||||
// .long 0xf19aee7c
|
||||
[self assert:instructions[8] operation:Operation::rlmix rA:28 rS:25 rB:21 mb:6 me:13 rc:TRUE];
|
||||
[self assert:instructions[9] operation:Operation::lfdu frD:16 rA:8 d:-13282];
|
||||
[self assertUndefined:instructions[10]];
|
||||
[self assertUndefined:instructions[11]];
|
||||
|
||||
// rlwimi. r8,r22,10,11,20
|
||||
// lfsu f20,-16191(r1)
|
||||
// stfs f29,-603(r17)
|
||||
// .long 0xe2b401cb
|
||||
[self assert:instructions[12] operation:Operation::rlwimix rA:8 rS:22 rB:10 mb:11 me:20 rc:TRUE];
|
||||
[self assert:instructions[13] operation:Operation::lfsu frD:20 rA:1 d:-16191];
|
||||
[self assert:instructions[14] operation:Operation::stfs frS:29 rA:17 d:-603];
|
||||
[self assertUndefined:instructions[15]];
|
||||
|
||||
// .long 0x433cb83d
|
||||
// rlwinm. r1,r2,5,29,0
|
||||
// rlwimi r13,r25,12,9,5
|
||||
// .long 0xb3117c5
|
||||
[self assertUndefined:instructions[16]];
|
||||
[self assert:instructions[17] operation:Operation::rlwinmx rA:1 rS:2 rB:5 mb:29 me:0 rc:TRUE];
|
||||
[self assert:instructions[18] operation:Operation::rlwimix rA:13 rS:25 rB:12 mb:9 me:5 rc:FALSE];
|
||||
[self assertUndefined:instructions[19]];
|
||||
|
||||
// stb r4,17594(r1)
|
||||
// lfsu f29,27344(r9)
|
||||
// cmpli cr0,1,r19,5236
|
||||
// rlwinm. r0,r17,24,13,19
|
||||
[self assert:instructions[20] operation:Operation::stb rS:4 rA:1 d:17594];
|
||||
[self assert:instructions[21] operation:Operation::lfsu frD:29 rA:9 d:27344];
|
||||
[self assert:instructions[22] operation:Operation::cmpli crfD:0 l:TRUE rA:19 uimm:5236];
|
||||
[self assert:instructions[23] operation:Operation::rlwinmx rA:0 rS:17 rB:24 mb:13 me:19 rc:TRUE];
|
||||
|
||||
// lha r24,9735(r10)
|
||||
// .long 0xe826acf4
|
||||
// beq+ cr5,0xffffffffffff91bc [at address 0x68]
|
||||
// oris r17,r3,53407
|
||||
[self assert:instructions[24] operation:Operation::lha rD:24 rA:10 d:9735];
|
||||
[self assertUndefined:instructions[25]];
|
||||
[self assert:instructions[26] operation:Operation::bcx bo:12 bi:22 bd:0xffff91bc - 0x68 lk:FALSE aa:FALSE];
|
||||
[self assert:instructions[27] operation:Operation::oris rA:17 rS:3 uimm:53407];
|
||||
|
||||
// xori r5,r17,61519
|
||||
// bl 0xfffffffffe1599e0 [at address 0x74]
|
||||
// dozi r25,r12,-26897
|
||||
// lha r25,29097(r17)
|
||||
[self assert:instructions[28] operation:Operation::xori rA:5 rS:17 uimm:61519];
|
||||
[self assert:instructions[29] operation:Operation::bx li:0xfe1599e0 - 0x74 lk:TRUE aa:FALSE];
|
||||
[self assert:instructions[30] operation:Operation::dozi rD:25 rA:12 simm:-26897];
|
||||
[self assert:instructions[31] operation:Operation::lha rD:25 rA:17 d:29097];
|
||||
}
|
||||
|
||||
@end
|
||||
336
OSBindings/Mac/Clock SignalTests/x86DecoderTests.mm
Normal file
336
OSBindings/Mac/Clock SignalTests/x86DecoderTests.mm
Normal file
@ -0,0 +1,336 @@
|
||||
//
|
||||
// x86DecoderTests.m
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 03/01/2021.
|
||||
// Copyright 2021 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#import <XCTest/XCTest.h>
|
||||
|
||||
#include <initializer_list>
|
||||
#include <vector>
|
||||
#include "../../../InstructionSets/x86/Decoder.hpp"
|
||||
|
||||
namespace {
|
||||
using Operation = CPU::Decoder::x86::Operation;
|
||||
using Instruction = CPU::Decoder::x86::Instruction;
|
||||
using Source = CPU::Decoder::x86::Source;
|
||||
using Size = CPU::Decoder::x86::Size;
|
||||
}
|
||||
|
||||
@interface x86DecoderTests : XCTestCase
|
||||
@end
|
||||
|
||||
/*!
|
||||
Tests 8086 decoding by throwing a bunch of randomly-generated
|
||||
word streams and checking that the result matches what I got from a
|
||||
disassembler elsewhere.
|
||||
*/
|
||||
@implementation x86DecoderTests {
|
||||
std::vector<Instruction> instructions;
|
||||
}
|
||||
|
||||
// MARK: - Specific instruction asserts.
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source destination:(Source)destination displacement:(int16_t)displacement {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
|
||||
XCTAssertEqual(instruction.source(), source);
|
||||
XCTAssertEqual(instruction.destination(), destination);
|
||||
XCTAssertEqual(instruction.displacement(), displacement);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source destination:(Source)destination displacement:(int16_t)displacement operand:(uint16_t)operand {
|
||||
[self assert:instruction operation:operation size:size source:source destination:destination displacement:displacement];
|
||||
XCTAssertEqual(instruction.operand(), operand);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source destination:(Source)destination operand:(uint16_t)operand {
|
||||
[self assert:instruction operation:operation size:size source:source destination:destination displacement:0 operand:operand];
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source destination:(Source)destination {
|
||||
[self assert:instruction operation:operation size:size source:source destination:destination displacement:0];
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size source:(Source)source {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
|
||||
XCTAssertEqual(instruction.source(), source);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size destination:(Source)destination {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
|
||||
XCTAssertEqual(instruction.destination(), destination);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size operand:(uint16_t)operand destination:(Source)destination {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size));
|
||||
XCTAssertEqual(instruction.destination(), destination);
|
||||
XCTAssertEqual(instruction.source(), Source::Immediate);
|
||||
XCTAssertEqual(instruction.operand(), operand);
|
||||
XCTAssertEqual(instruction.displacement(), 0);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation displacement:(int16_t)displacement {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.displacement(), displacement);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation operand:(uint16_t)operand {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.operand(), operand);
|
||||
XCTAssertEqual(instruction.displacement(), 0);
|
||||
}
|
||||
|
||||
- (void)assert:(Instruction &)instruction operation:(Operation)operation segment:(uint16_t)segment offset:(uint16_t)offset {
|
||||
XCTAssertEqual(instruction.operation, operation);
|
||||
XCTAssertEqual(instruction.segment(), segment);
|
||||
XCTAssertEqual(instruction.offset(), offset);
|
||||
}
|
||||
|
||||
// MARK: - Decoder
|
||||
|
||||
- (void)decode:(const std::initializer_list<uint8_t> &)stream {
|
||||
// Decode by offering up all data at once.
|
||||
CPU::Decoder::x86::Decoder decoder(CPU::Decoder::x86::Model::i8086);
|
||||
instructions.clear();
|
||||
const uint8_t *byte = stream.begin();
|
||||
while(byte != stream.end()) {
|
||||
const auto [size, next] = decoder.decode(byte, stream.end() - byte);
|
||||
if(size <= 0) break;
|
||||
instructions.push_back(next);
|
||||
byte += size;
|
||||
}
|
||||
|
||||
// Grab a byte-at-a-time decoding and check that it matches the previous.
|
||||
{
|
||||
CPU::Decoder::x86::Decoder decoder(CPU::Decoder::x86::Model::i8086);
|
||||
|
||||
auto previous_instruction = instructions.begin();
|
||||
for(auto item: stream) {
|
||||
const auto [size, next] = decoder.decode(&item, 1);
|
||||
if(size > 0) {
|
||||
XCTAssert(next == *previous_instruction);
|
||||
++previous_instruction;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// MARK: - Tests
|
||||
|
||||
- (void)testSequence1 {
|
||||
// Sequences the Online Disassembler believes to exist but The 8086 Book does not:
|
||||
//
|
||||
// 0x6a 0x65 push $65
|
||||
// 0x65 0x6d gs insw (%dx),%es:(%di)
|
||||
// 0x67 0x61 addr32 popa
|
||||
// 0x6c insb (%dx), %es:(%di)
|
||||
// 0xc9 leave
|
||||
//
|
||||
[self decode:{
|
||||
0x2d, 0x77, 0xea, 0x72, 0xfc, 0x4b, 0xb5, 0x28, 0xc3, 0xca, 0x26, 0x48, /* 0x65, 0x6d, */ 0x7b, 0x9f,
|
||||
0xc2, 0x65, 0x42, 0x4e, 0xef, 0x70, 0x20, 0x94, 0xc4, 0xd4, 0x93, 0x43, 0x3c, 0x8e, /* 0x6a, 0x65, */
|
||||
0x1a, 0x78, 0x45, 0x10, 0x7f, 0x3c, 0x19, 0x5a, 0x16, 0x31, 0x64, 0x2c, 0xe7, 0xc6, 0x7d, 0xb0,
|
||||
0xb5, 0x49, /* 0x67, 0x61, */ 0xba, 0xc0, 0xcb, 0x14, 0x7e, 0x71, 0xd0, 0x50, 0x78, 0x3d, 0x03, 0x1d,
|
||||
0xe5, 0xc9, 0x97, 0xc3, 0x9b, 0xe6, 0xd3, /* 0x6c, */ 0x58, 0x4d, 0x76, 0x80, 0x44, 0xd6, 0x9f, 0xa5,
|
||||
0xbd, 0xa1, 0x12, 0xc5, 0x29, /* 0xc9, */ 0x9e, 0xd8, 0xf3, 0xcf, 0x92, 0x39, 0x5d, 0x90, 0x15, 0xc3,
|
||||
0xb8, 0xad, 0xe8, 0xc8, 0x16, 0x4a, 0xb0, 0x9e, 0xf9, 0xbf, 0x56, 0xea, 0x4e, 0xfd, 0xe4, 0x5a,
|
||||
0x23, 0xaa, 0x2c, 0x5b, 0x2a, 0xd2, 0xf7, 0x5f, 0x18, 0x86, 0x90, 0x25, 0x64, 0xb7, 0xc3
|
||||
}];
|
||||
|
||||
// 63 instructions are expected.
|
||||
XCTAssertEqual(instructions.size(), 63);
|
||||
|
||||
// sub $0xea77,%ax
|
||||
// jb 0x00000001
|
||||
// dec %bx
|
||||
// mov $0x28,%ch
|
||||
[self assert:instructions[0] operation:Operation::SUB size:2 operand:0xea77 destination:Source::AX];
|
||||
[self assert:instructions[1] operation:Operation::JB displacement:0xfffc];
|
||||
[self assert:instructions[2] operation:Operation::DEC size:2 source:Source::BX destination:Source::BX];
|
||||
[self assert:instructions[3] operation:Operation::MOV size:1 operand:0x28 destination:Source::CH];
|
||||
|
||||
// ret
|
||||
// lret $0x4826
|
||||
// [[ omitted: gs insw (%dx),%es:(%di) ]]
|
||||
// jnp 0xffffffaf
|
||||
// ret $0x4265
|
||||
[self assert:instructions[4] operation:Operation::RETN];
|
||||
[self assert:instructions[5] operation:Operation::RETF operand:0x4826];
|
||||
[self assert:instructions[6] operation:Operation::JNP displacement:0xff9f];
|
||||
[self assert:instructions[7] operation:Operation::RETN operand:0x4265];
|
||||
|
||||
// dec %si
|
||||
// out %ax,(%dx)
|
||||
// jo 0x00000037
|
||||
// xchg %ax,%sp
|
||||
[self assert:instructions[8] operation:Operation::DEC size:2 source:Source::SI destination:Source::SI];
|
||||
[self assert:instructions[9] operation:Operation::OUT size:2 source:Source::AX destination:Source::DX];
|
||||
[self assert:instructions[10] operation:Operation::JO displacement:0x20];
|
||||
[self assert:instructions[11] operation:Operation::XCHG size:2 source:Source::AX destination:Source::SP];
|
||||
|
||||
// ODA has:
|
||||
// c4 (bad)
|
||||
// d4 93 aam $0x93
|
||||
//
|
||||
// That assumes that upon discovering that the d4 doesn't make a valid LES,
|
||||
// it can become an instruction byte. I'm not persuaded. So I'm taking:
|
||||
//
|
||||
// c4 d4 (bad)
|
||||
// 93 XCHG AX, BX
|
||||
[self assert:instructions[12] operation:Operation::Invalid];
|
||||
[self assert:instructions[13] operation:Operation::XCHG size:2 source:Source::AX destination:Source::BX];
|
||||
|
||||
// inc %bx
|
||||
// cmp $0x8e,%al
|
||||
// [[ omitted: push $0x65 ]]
|
||||
// sbb 0x45(%bx,%si),%bh
|
||||
// adc %bh,0x3c(%bx)
|
||||
[self assert:instructions[14] operation:Operation::INC size:2 source:Source::BX destination:Source::BX];
|
||||
[self assert:instructions[15] operation:Operation::CMP size:1 operand:0x8e destination:Source::AL];
|
||||
[self assert:instructions[16] operation:Operation::SBB size:1 source:Source::IndBXPlusSI destination:Source::BH displacement:0x45];
|
||||
[self assert:instructions[17] operation:Operation::ADC size:1 source:Source::BH destination:Source::IndBX displacement:0x3c];
|
||||
|
||||
// sbb %bx,0x16(%bp,%si)
|
||||
// xor %sp,0x2c(%si)
|
||||
// out %ax,$0xc6
|
||||
// jge 0xffffffe0
|
||||
[self assert:instructions[18] operation:Operation::SBB size:2 source:Source::BX destination:Source::IndBPPlusSI displacement:0x16];
|
||||
[self assert:instructions[19] operation:Operation::XOR size:2 source:Source::SP destination:Source::IndSI displacement:0x2c];
|
||||
[self assert:instructions[20] operation:Operation::OUT size:2 source:Source::AX destination:Source::DirectAddress operand:0xc6];
|
||||
[self assert:instructions[21] operation:Operation::JNL displacement:0xffb0];
|
||||
|
||||
// mov $0x49,%ch
|
||||
// [[ omitted: addr32 popa ]]
|
||||
// mov $0xcbc0,%dx
|
||||
// adc $0x7e,%al
|
||||
// jno 0x0000000b
|
||||
[self assert:instructions[22] operation:Operation::MOV size:1 operand:0x49 destination:Source::CH];
|
||||
[self assert:instructions[23] operation:Operation::MOV size:2 operand:0xcbc0 destination:Source::DX];
|
||||
[self assert:instructions[24] operation:Operation::ADC size:1 operand:0x7e destination:Source::AL];
|
||||
[self assert:instructions[25] operation:Operation::JNO displacement:0xffd0];
|
||||
|
||||
// push %ax
|
||||
// js 0x0000007b
|
||||
// add (%di),%bx
|
||||
// in $0xc9,%ax
|
||||
[self assert:instructions[26] operation:Operation::PUSH size:2 source:Source::AX];
|
||||
[self assert:instructions[27] operation:Operation::JS displacement:0x3d];
|
||||
[self assert:instructions[28] operation:Operation::ADD size:2 source:Source::IndDI destination:Source::BX];
|
||||
[self assert:instructions[29] operation:Operation::IN size:2 source:Source::DirectAddress destination:Source::AX operand:0xc9];
|
||||
|
||||
// xchg %ax,%di
|
||||
// ret
|
||||
// fwait
|
||||
// out %al,$0xd3
|
||||
[self assert:instructions[30] operation:Operation::XCHG size:2 source:Source::AX destination:Source::DI];
|
||||
[self assert:instructions[31] operation:Operation::RETN];
|
||||
[self assert:instructions[32] operation:Operation::WAIT];
|
||||
[self assert:instructions[33] operation:Operation::OUT size:1 source:Source::AL destination:Source::DirectAddress operand:0xd3];
|
||||
|
||||
// [[ omitted: insb (%dx),%es:(%di) ]]
|
||||
// pop %ax
|
||||
// dec %bp
|
||||
// jbe 0xffffffcc
|
||||
// inc %sp
|
||||
[self assert:instructions[34] operation:Operation::POP size:2 destination:Source::AX];
|
||||
[self assert:instructions[35] operation:Operation::DEC size:2 source:Source::BP destination:Source::BP];
|
||||
[self assert:instructions[36] operation:Operation::JBE displacement:0xff80];
|
||||
[self assert:instructions[37] operation:Operation::INC size:2 source:Source::SP destination:Source::SP];
|
||||
|
||||
// (bad)
|
||||
// lahf
|
||||
// movsw %ds:(%si),%es:(%di)
|
||||
// mov $0x12a1,%bp
|
||||
[self assert:instructions[38] operation:Operation::Invalid];
|
||||
[self assert:instructions[39] operation:Operation::LAHF];
|
||||
[self assert:instructions[40] operation:Operation::MOVS size:2];
|
||||
[self assert:instructions[41] operation:Operation::MOV size:2 operand:0x12a1 destination:Source::BP];
|
||||
|
||||
// lds (%bx,%di),%bp
|
||||
// [[ omitted: leave ]]
|
||||
// sahf
|
||||
// fdiv %st(3),%st
|
||||
// iret
|
||||
[self assert:instructions[42] operation:Operation::LDS size:2];
|
||||
[self assert:instructions[43] operation:Operation::SAHF];
|
||||
[self assert:instructions[44] operation:Operation::ESC];
|
||||
[self assert:instructions[45] operation:Operation::IRET];
|
||||
|
||||
// xchg %ax,%dx
|
||||
// cmp %bx,-0x70(%di)
|
||||
// adc $0xb8c3,%ax
|
||||
// lods %ds:(%si),%ax
|
||||
[self assert:instructions[46] operation:Operation::XCHG size:2 source:Source::AX destination:Source::DX];
|
||||
[self assert:instructions[47] operation:Operation::CMP size:2 source:Source::BX destination:Source::IndDI displacement:0xff90];
|
||||
[self assert:instructions[48] operation:Operation::ADC size:2 operand:0xb8c3 destination:Source::AX];
|
||||
[self assert:instructions[49] operation:Operation::LODS size:2];
|
||||
|
||||
// call 0x0000172d
|
||||
// dec %dx
|
||||
// mov $0x9e,%al
|
||||
// stc
|
||||
[self assert:instructions[50] operation:Operation::CALLD operand:0x16c8];
|
||||
[self assert:instructions[51] operation:Operation::DEC size:2 source:Source::DX destination:Source::DX];
|
||||
[self assert:instructions[52] operation:Operation::MOV size:1 operand:0x9e destination:Source::AL];
|
||||
[self assert:instructions[53] operation:Operation::STC];
|
||||
|
||||
// mov $0xea56,%di
|
||||
// dec %si
|
||||
// std
|
||||
// in $0x5a,%al
|
||||
[self assert:instructions[54] operation:Operation::MOV size:2 operand:0xea56 destination:Source::DI];
|
||||
[self assert:instructions[55] operation:Operation::DEC size:2 source:Source::SI destination:Source::SI];
|
||||
[self assert:instructions[56] operation:Operation::STD];
|
||||
[self assert:instructions[57] operation:Operation::IN size:1 source:Source::DirectAddress destination:Source::AL operand:0x5a];
|
||||
|
||||
// and 0x5b2c(%bp,%si),%bp
|
||||
// sub %dl,%dl
|
||||
// negw 0x18(%bx)
|
||||
// xchg %dl,0x6425(%bx,%si)
|
||||
[self assert:instructions[58] operation:Operation::AND size:2 source:Source::IndBPPlusSI destination:Source::BP displacement:0x5b2c];
|
||||
[self assert:instructions[59] operation:Operation::SUB size:1 source:Source::DL destination:Source::DL];
|
||||
[self assert:instructions[60] operation:Operation::NEG size:2 source:Source::IndBX destination:Source::IndBX displacement:0x18];
|
||||
[self assert:instructions[61] operation:Operation::XCHG size:1 source:Source::IndBXPlusSI destination:Source::DL displacement:0x6425];
|
||||
|
||||
// mov $0xc3,%bh
|
||||
[self assert:instructions[62] operation:Operation::MOV size:1 operand:0xc3 destination:Source::BH];
|
||||
}
|
||||
|
||||
- (void)test83 {
|
||||
[self decode:{
|
||||
0x83, 0x10, 0x80, // adcw $0xff80,(%bx,%si)
|
||||
0x83, 0x3b, 0x04, // cmpw $0x4,(%bp,%di)
|
||||
0x83, 0x2f, 0x09, // subw $0x9,(%bx)
|
||||
}];
|
||||
|
||||
XCTAssertEqual(instructions.size(), 3);
|
||||
[self assert:instructions[0] operation:Operation::ADC size:2 source:Source::Immediate destination:Source::IndBXPlusSI operand:0xff80];
|
||||
[self assert:instructions[1] operation:Operation::CMP size:2 source:Source::Immediate destination:Source::IndBPPlusDI operand:0x4];
|
||||
[self assert:instructions[2] operation:Operation::SUB size:2 source:Source::Immediate destination:Source::IndBX operand:0x9];
|
||||
}
|
||||
|
||||
- (void)testFar {
|
||||
[self decode:{
|
||||
0x9a, 0x12, 0x34, 0x56, 0x78, // lcall 0x7856, 0x3412
|
||||
}];
|
||||
|
||||
XCTAssertEqual(instructions.size(), 1);
|
||||
[self assert:instructions[0] operation:Operation::CALLF segment:0x7856 offset:0x3412];
|
||||
}
|
||||
|
||||
@end
|
||||
Loading…
Reference in New Issue
Block a user