diff --git a/Components/9918/9918.cpp b/Components/9918/9918.cpp
index 9b53c4aa6..1bc8465d0 100644
--- a/Components/9918/9918.cpp
+++ b/Components/9918/9918.cpp
@@ -86,6 +86,16 @@ struct ReverseTable {
 
 constexpr ReverseTable reverse_table;
 
+template <Personality personality> constexpr int vram_access_delay() {
+	// This seems to be correct for all currently-modelled VDPs;
+	// it's the delay between an external device scheduling a
+	// read or write and the very first time that can occur
+	// (though, in practice, it won't happen until the next
+	// external slot after this number of cycles after the
+	// device has requested the read or write).
+	return 6;
+}
+
 }
 
 template <Personality personality>
@@ -549,7 +559,7 @@ void TMS9918<personality>::write(int address, uint8_t value) {
 		// Enqueue the write to occur at the next available slot.
 		this->read_ahead_buffer_ = value;
 		this->queued_access_ = MemoryAccess::Write;
-		this->cycles_until_access_ = this->vram_access_delay();
+		this->cycles_until_access_ = vram_access_delay<personality>();
 
 		return;
 	}
@@ -664,7 +674,7 @@ void TMS9918<personality>::write(int address, uint8_t value) {
 			// A read request is enqueued upon setting the address; conversely a write
 			// won't be enqueued unless and until some actual data is supplied.
 			this->queued_access_ = MemoryAccess::Read;
-			this->cycles_until_access_ = this->vram_access_delay();
+			this->cycles_until_access_ = vram_access_delay<personality>();
 		}
 		this->master_system_.cram_is_selected = false;
 	}
diff --git a/Components/9918/Implementation/9918Base.hpp b/Components/9918/Implementation/9918Base.hpp
index 3cf571e65..396920ee9 100644
--- a/Components/9918/Implementation/9918Base.hpp
+++ b/Components/9918/Implementation/9918Base.hpp
@@ -172,15 +172,6 @@ template <Personality personality> struct Base {
 	MemoryAccess queued_access_ = MemoryAccess::None;
 	int cycles_until_access_ = 0;
 	int minimum_access_column_ = 0;
-	int vram_access_delay() {
-		// This seems to be correct for all currently-modelled VDPs;
-		// it's the delay between an external device scheduling a
-		// read or write and the very first time that can occur
-		// (though, in practice, it won't happen until the next
-		// external slot after this number of cycles after the
-		// device has requested the read or write).
-		return 6;
-	}
 
 	// Holds the main status register.
 	uint8_t status_ = 0;