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Attempts to clock the disk controller.

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This commit is contained in:
Thomas Harte 2021-10-05 15:38:56 -07:00
parent ad4afcdcd5
commit 18631399ad
2 changed files with 27 additions and 2 deletions
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18
Machines/Amiga/Chipset.cpp
View File

@ -15,6 +15,7 @@
#include <algorithm>
#include <cassert>
using namespace Amiga;
namespace {
@ -43,6 +44,7 @@ Chipset::Chipset(MemoryMap &map, int input_clock_rate) :
cia_b_handler_(disk_controller_),
cia_a(cia_a_handler_),
cia_b(cia_b_handler_) {
disk_controller_.set_clocking_hint_observer(this);
}
Chipset::Changes Chipset::run_for(HalfCycles length) {
@ -412,10 +414,19 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
cia_b.run_for(e_clocks);
}
// Propagate TOD updates to the CIAs, and feed their new interrupt
// outputs back to here.
cia_a.advance_tod(vsyncs);
cia_b.advance_tod(hsyncs);
set_cia_interrupts(cia_a.get_interrupt_line(), cia_b.get_interrupt_line());
// Update the disk controller, if any drives are active.
if(!disk_controller_is_sleeping_) {
disk_controller_.run_for(changes.duration.cycles());
}
// Record the interrupt level.
// TODO: is this useful?
changes.interrupt_level = interrupt_level_;
return changes;
}
@ -994,6 +1005,13 @@ uint8_t Chipset::CIABHandler::get_port_input(MOS::MOS6526::Port) {
return 0xff;
}
// MARK: - ClockingHintObserver.
void Chipset::set_component_prefers_clocking(ClockingHint::Source *, ClockingHint::Preference preference) {
disk_controller_is_sleeping_ = preference == ClockingHint::Preference::None;
LOG("Disk controller is " << (disk_controller_is_sleeping_ ? "sleeping" : "awake"));
}
// MARK: - Disk Controller.
Chipset::DiskController::DiskController(Cycles clock_rate) :

11
Machines/Amiga/Chipset.hpp
View File

@ -13,6 +13,7 @@
#include <cstdint>
#include "../../Activity/Source.hpp"
#include "../../ClockReceiver/ClockingHintSource.hpp"
#include "../../Components/6526/6526.hpp"
#include "../../Outputs/CRT/CRT.hpp"
#include "../../Processors/68000/68000.hpp"
@ -59,7 +60,7 @@ enum class DMAFlag: uint16_t {
BlitterBusy = 1 << 14,
};
class Chipset {
class Chipset: private ClockingHint::Observer {
public:
Chipset(MemoryMap &memory_map, int input_clock_rate);
@ -218,13 +219,17 @@ class Chipset {
// MARK: - Disk drives.
class DiskController: private Storage::Disk::Controller {
class DiskController: public Storage::Disk::Controller {
public:
DiskController(Cycles clock_rate);
void set_mtr_sel_side_dir_step(uint8_t);
uint8_t get_rdy_trk0_wpro_chng();
void run_for(Cycles duration) {
Storage::Disk::Controller::run_for(duration);
}
private:
void process_input_bit(int value) final;
void process_index_hole() final;
@ -235,6 +240,8 @@ class Chipset {
uint32_t previous_select_ = 0;
} disk_controller_;
void set_component_prefers_clocking(ClockingHint::Source *, ClockingHint::Preference) final;
bool disk_controller_is_sleeping_ = false;
class DiskDMA: public DMADevice<1> {
public: