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The soft switch is LCBANK2, not LCBANK1.

[This also jimmys the IIgs into always entering its extended self test, for now]
This commit is contained in:
Thomas Harte 2020-11-30 22:35:51 -05:00
parent 6000bd3a5e
commit 187f507532
4 changed files with 21 additions and 21 deletions

View File

@ -202,9 +202,11 @@ template <Analyser::Static::AppleII::Target::Model model> class ConcreteMachine:
uint8_t *const ram = zero_state ? aux_ram_ : ram_;
uint8_t *const rom = is_iie() ? &rom_[3840] : rom_.data();
// Which way the region here is mapped to be banks 1 and 2 is
// arbitrary.
page(0xd0, 0xe0,
language_state.read ? &ram[language_state.bank1 ? 0xd000 : 0xc000] : rom,
language_state.write ? nullptr : &ram[language_state.bank1 ? 0xd000 : 0xc000]);
language_state.read ? &ram[language_state.bank2 ? 0xd000 : 0xc000] : rom,
language_state.write ? nullptr : &ram[language_state.bank2 ? 0xd000 : 0xc000]);
page(0xe0, 0x100,
language_state.read ? &ram[0xe000] : &rom[0x1000],
@ -525,7 +527,7 @@ template <Analyser::Static::AppleII::Target::Model model> class ConcreteMachine:
// The IIe-only state reads follow...
#define IIeSwitchRead(s) *value = get_keyboard_input(); if(is_iie()) *value = (*value & 0x7f) | (s ? 0x80 : 0x00);
case 0xc011: IIeSwitchRead(language_card_.state().bank1); break;
case 0xc011: IIeSwitchRead(language_card_.state().bank2); break;
case 0xc012: IIeSwitchRead(language_card_.state().read); break;
case 0xc013: IIeSwitchRead(auxiliary_switches_.switches().read_auxiliary_memory); break;
case 0xc014: IIeSwitchRead(auxiliary_switches_.switches().write_auxiliary_memory); break;

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@ -22,9 +22,9 @@ template <typename Machine> class LanguageCardSwitches {
public:
struct State {
/// When RAM is visible in the range $D000$FFFF:
/// @c true indicates that bank 1 should be used;
/// @c false indicates bank 2.
bool bank1 = false;
/// @c true indicates that bank 2 should be used;
/// @c false indicates bank 1.
bool bank2 = true;
/// @c true indicates that RAM should be readable in the range $D000$FFFF;
/// @c false indicates ROM should be readable.
@ -36,7 +36,7 @@ template <typename Machine> class LanguageCardSwitches {
bool operator != (const State &rhs) const {
return
bank1 != rhs.bank1 ||
bank2 != rhs.bank2 ||
read != rhs.read ||
write != rhs.write;
}
@ -51,7 +51,7 @@ template <typename Machine> class LanguageCardSwitches {
// Quotes below taken from Understanding the Apple II, p. 5-28 and 5-29.
// "A3 controls the 4K bank selection"; 0 = bank 2, 1 = bank 1.
state_.bank1 = address & 8;
state_.bank2 = !(address & 8);
// "Access to $C080, $C083, $C084, $0087, $C088, $C08B, $C08C, or $C08F sets the READ ENABLE flip-flop"
// (other accesses reset it)
@ -85,8 +85,8 @@ template <typename Machine> class LanguageCardSwitches {
// Bit 3: 1 => enable ROM, 0 => enable RAM.
state_.read = !(value & 0x08);
// Bit 2: 1 => select bank 1, 0 => select bank 2.
state_.bank1 = value & 0x04;
// Bit 2: 1 => select bank 2, 0 => select bank 1. [per errata to the Hardware Reference, which lists them the other way around]
state_.bank2 = value & 0x04;
if(previous_state != state_) {
machine_.set_language_card_paging();
@ -96,7 +96,7 @@ template <typename Machine> class LanguageCardSwitches {
uint8_t get_state() const {
return
(state_.read ? 0x00 : 0x08) |
(state_.bank1 ? 0x04 : 0x00);
(state_.bank2 ? 0x04 : 0x00);
}
private:

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@ -303,7 +303,7 @@ class ConcreteMachine:
#define LanguageRead(s) SwitchRead(language_card_switches().state().s)
#define AuxiliaryRead(s) SwitchRead(auxiliary_switches().switches().s)
#define VideoRead(s) *value = video_.last_valid()->s ? 0x80 : 0x00
case Read(0xc011): LanguageRead(bank1); break;
case Read(0xc011): LanguageRead(bank2); break;
case Read(0xc012): LanguageRead(read); break;
case Read(0xc013): AuxiliaryRead(read_auxiliary_memory); break;
case Read(0xc014): AuxiliaryRead(write_auxiliary_memory); break;
@ -458,7 +458,7 @@ class ConcreteMachine:
// Analogue inputs. All TODO.
case Read(0xc060): case Read(0xc061): case Read(0xc062): case Read(0xc063):
// Joystick buttons (and keyboard modifiers).
*value = 0x00;
*value = 0x80;
break;
case Read(0xc064): case Read(0xc065): case Read(0xc066): case Read(0xc067):
@ -681,7 +681,7 @@ class ConcreteMachine:
if(address_suffix < 0xc080) {
// TODO: all other IO accesses.
printf("Unhandled IO %s: %04x\n", is_read ? "read" : "write", address_suffix);
assert(false);
// assert(false);
}
}
}
@ -715,12 +715,12 @@ class ConcreteMachine:
if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
assert(address);
}
// if(address == 0xe115fe || address == 0xe115ff) {
// if(address >= 0xE11700 && address < 0xe11b00) {
// printf("%06x %s %02x%s\n", address, isReadOperation(operation) ? "->" : "<-", *value,
// operation == CPU::WDC65816::BusOperation::ReadOpcode ? " [*]" : "");
// }
// log |= (operation == CPU::WDC65816::BusOperation::ReadOpcode) && (address == 0xfc0d50);
// log &= !((operation == CPU::WDC65816::BusOperation::ReadOpcode) && ((address >= 0xfc0d5b) || (address < 0xfc0d50)));
log = (operation == CPU::WDC65816::BusOperation::ReadOpcode) && (address >= 0xff6a2c) && (address < 0xff6a9c);
// log &= !((operation == CPU::WDC65816::BusOperation::ReadOpcode) && ((address >= 0xff9a2c) || (address < 0xff6a2c)));
if(log) {
printf("%06x %s %02x", address, isReadOperation(operation) ? "->" : "<-", *value);
if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {

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@ -255,10 +255,8 @@ class MemoryMap {
// All references below are to 0xc000, 0xd000 and 0xe000 but should
// work regardless of bank.
// This assumes bank 1 is the one before bank 2 when RAM is linear;
// also cf. the errata in tech note #30 — this flag enabled means bank 2;
// it disabled means bank 1.
uint8_t *const lower_ram_bank = ram - (language_state.bank1 ? 0x0000 : 0x1000);
// This assumes bank 1 is the one before bank 2 when RAM is linear.
uint8_t *const lower_ram_bank = ram - (language_state.bank2 ? 0x0000 : 0x1000);
// Crib the ROM pointer from a page it's always visible on.
const uint8_t *const rom = &regions[region_map[0xffd0]].read[0xffd000] - ((bank_base << 8) + 0xd000);