6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-12-25 03:32:01 +00:00
Code Issues Projects Releases Wiki Activity

Correct extension ROM visibility.

Browse Source
This commit is contained in:
Thomas Harte 2023-01-13 22:22:58 -05:00
parent 5f85074caa
commit 18def0c97d
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Machines/MSX/MSX.cpp
View File

@ -284,10 +284,10 @@ class ConcreteMachine:
memory_slots_[RAMMemorySlot].set_source(ram_plus); memory_slots_[RAMMemorySlot].set_source(ram_plus);
memory_slots_[RAMMemorySlot].template map<MemorySlot::AccessType::ReadWrite>(RAMMemorySubSlot, 0, 0, 65536); memory_slots_[RAMMemorySlot].template map<MemorySlot::AccessType::ReadWrite>(RAMMemorySubSlot, 0, 0, 65536);
memory_slots_[RAMMemorySlot].map(ExtensionROMSubSlot, 0, 0, 32768); memory_slots_[RAMMemorySlot].map(ExtensionROMSubSlot, RAMSize, 0, 32768);
} else { } else {
memory_slots_[RAMMemorySlot].resize_source(65536); memory_slots_[RAMMemorySlot].resize_source(65536);
memory_slots_[RAMMemorySlot].template map<MemorySlot::AccessType::ReadWrite>(RAMMemorySubSlot, RAMSize, 0, 65536); memory_slots_[RAMMemorySlot].template map<MemorySlot::AccessType::ReadWrite>(RAMMemorySubSlot, 0, 0, 65536);
} }
// Add a disk cartridge if any disks were supplied. // Add a disk cartridge if any disks were supplied.
@ -612,7 +612,9 @@ class ConcreteMachine:
break; break;
case 0xfc: case 0xfd: case 0xfe: case 0xff: case 0xfc: case 0xfd: case 0xfe: case 0xff:
// printf("RAM banking %02x: %02x\n", port, *cycle.value); // 1. Propagate to all handlers.
// 2. Apply to RAM.
// printf("RAM banking %02x: %02x\n", port, *cycle.value);
break; break;
} }
} break; } break;