6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
Code Issues Projects Releases Wiki Activity

Minor: ensure AY registers *read* as 0 from reset, as well as being 0.

Browse Source
This commit is contained in:
Thomas Harte 2018-06-01 19:48:42 -04:00
parent 0833412df9
commit 1a9cea050e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Components/AY38910/AY38910.hpp
View File

@ -92,7 +92,7 @@ class AY38910: public ::Outputs::Speaker::SampleSource {
Concurrency::DeferringAsyncTaskQueue &task_queue_;
int selected_register_ = 0;
uint8_t registers_[16];
uint8_t registers_[16] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
uint8_t output_registers_[16] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
uint8_t port_inputs_[2];