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Move some way towards MOVE.

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This commit is contained in:
Thomas Harte 2022-05-18 21:00:10 -04:00
parent 44ae084794
commit 1b87626b82
1 changed files with 37 additions and 3 deletions
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40
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -45,9 +45,11 @@ enum ExecutionState: int {
Perform_np, Perform_np,
Perform_np_n, Perform_np_n,
// MOVE has unique bus usage, so has a specialised state. // MOVE has unique bus usage, so has specialised states.
MOVEWrite, MOVEw,
MOVEwRegisterDirect,
MOVEwAddressRegisterIndirectWithPostincrement,
}; };
// MARK: - The state machine. // MARK: - The state machine.
@ -240,6 +242,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
} }
break; break;
CASE(MOVEw)
perform_state_ = MOVEw;
break;
default: default:
assert(false); assert(false);
} }
@ -321,7 +327,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
break; break;
// //
// Various forms of perform. // Various generic forms of perform.
// //
#define MoveToWritePhase() \ #define MoveToWritePhase() \
next_operand_ = operand_flags_ >> 3; \ next_operand_ = operand_flags_ >> 3; \
@ -343,6 +349,34 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
#undef MoveToWritePhase #undef MoveToWritePhase
//
// Specific forms of perform.
//
BeginState(MOVEw):
switch(instruction_.mode(1)) {
case Mode::DataRegisterDirect:
case Mode::AddressRegisterDirect:
MoveToState(MOVEwRegisterDirect);
case Mode::AddressRegisterIndirectWithPostincrement:
MoveToState(MOVEwAddressRegisterIndirectWithPostincrement);
default: assert(false);
}
BeginState(MOVEwRegisterDirect):
registers_[instruction_.lreg(1)].w = operand_[1].w;
Prefetch(); // np
MoveToState(Decode);
BeginState(MOVEwAddressRegisterIndirectWithPostincrement):
// TODO: nw
assert(false);
Prefetch() // np
MoveToState(Decode);
// Various states TODO. // Various states TODO.
#define TODOState(x) \ #define TODOState(x) \
BeginState(x): [[fallthrough]]; BeginState(x): [[fallthrough]];