diff --git a/InstructionSets/M68k/Decoder.cpp b/InstructionSets/M68k/Decoder.cpp index 001c34020..a60735c49 100644 --- a/InstructionSets/M68k/Decoder.cpp +++ b/InstructionSets/M68k/Decoder.cpp @@ -513,6 +513,12 @@ template ::OpT op> uint32_t Predecoder::invali switch(op) { default: break; + case OpT(Operation::TRAPcc): + return ~TwoOperandMask< + Ext | NoOperand, + Ext | NoOperand + >::value; + case OpT(Operation::Bccl): case OpT(Operation::BSRl): return ~OneOperandMask< Imm @@ -1064,6 +1070,29 @@ template ::OpT op, bool validate> Preinstruction Pred return validated(addressing_mode, ea_register); } + // + // MARK: TRAPcc + // + // Has 0, 1 or 2 following words, neither of which contributes to operation. + // + case OpT(Operation::TRAPcc): { + switch(instruction & 7) { + default: return Preinstruction(); + + // No extension. + case 4: return validated(); + + // Word-sized extension. + case 2: return validated(AddressingMode::ExtensionWord); + + // DWord-sized extension (which is encoded as two extension operands). + case 3: + return validated( + AddressingMode::ExtensionWord, 0, + AddressingMode::ExtensionWord, 0); + } + } + // // MARK: PACK // @@ -1076,6 +1105,7 @@ template ::OpT op, bool validate> Preinstruction Pred // TODO; need to square the wheel on a prima-facie three operands. return Preinstruction(); + // // MARK: DIVl //