6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-07-01 14:29:51 +00:00
Code Issues Projects Releases Wiki Activity

Stores the colour palette, uses entry 0 as my new always output.

Browse Source
This commit is contained in:
Thomas Harte 2021-07-26 18:59:11 -04:00
parent 3832acf6e3
commit 1d03bc560a
2 changed files with 12 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
Machines/Amiga/Chipset.cpp
View File

@ -108,7 +108,7 @@ Chipset::Changes Chipset::run_for(HalfCycles length) {
uint16_t *const pixels = reinterpret_cast<uint16_t *>(crt_.begin_data(2)); uint16_t *const pixels = reinterpret_cast<uint16_t *>(crt_.begin_data(2));
if(pixels) { if(pixels) {
*pixels = 0xffff; *pixels = palette_[0];
} }
crt_.output_data((final_x - start_x) * 4, 1); crt_.output_data((final_x - start_x) * 4, 1);
} }
@ -162,7 +162,7 @@ void Chipset::update_interrupts() {
void Chipset::perform(const CPU::MC68000::Microcycle &cycle) { void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
using Microcycle = CPU::MC68000::Microcycle; using Microcycle = CPU::MC68000::Microcycle;
#define RW(address) (address & 0xffe) | ((cycle.operation & Microcycle::Read) << 12) #define RW(address) address | ((cycle.operation & Microcycle::Read) << 12)
#define Read(address) address | (Microcycle::Read << 12) #define Read(address) address | (Microcycle::Read << 12)
#define Write(address) address #define Write(address) address
@ -175,7 +175,8 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
} \ } \
} }
switch(RW(*cycle.address)) { const uint32_t register_address = *cycle.address & 0xffe;
switch(RW(register_address)) {
default: default:
LOG("Unimplemented chipset " << (cycle.operation & Microcycle::Read ? "read" : "write") << " " << PADHEX(6) << *cycle.address); LOG("Unimplemented chipset " << (cycle.operation & Microcycle::Read ? "read" : "write") << " " << PADHEX(6) << *cycle.address);
assert(false); assert(false);
@ -410,9 +411,13 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
case Write(0x1a0): case Write(0x1a2): case Write(0x1a4): case Write(0x1a6): case Write(0x1a0): case Write(0x1a2): case Write(0x1a4): case Write(0x1a6):
case Write(0x1a8): case Write(0x1aa): case Write(0x1ac): case Write(0x1ae): case Write(0x1a8): case Write(0x1aa): case Write(0x1ac): case Write(0x1ae):
case Write(0x1b0): case Write(0x1b2): case Write(0x1b4): case Write(0x1b6): case Write(0x1b0): case Write(0x1b2): case Write(0x1b4): case Write(0x1b6):
case Write(0x1b8): case Write(0x1ba): case Write(0x1bc): case Write(0x1be): case Write(0x1b8): case Write(0x1ba): case Write(0x1bc): case Write(0x1be): {
LOG("TODO: colour palette; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address); LOG("Colour palette; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
break;
uint8_t *const entry = reinterpret_cast<uint8_t *>(&palette_[(register_address - 0x180) >> 1]);
entry[0] = cycle.value8_high();
entry[1] = cycle.value8_low();
} break;
} }
#undef ApplySetClear #undef ApplySetClear

1
Machines/Amiga/Chipset.hpp
View File

@ -92,6 +92,7 @@ class Chipset {
// MARK: - Pixel output. // MARK: - Pixel output.
Outputs::CRT::CRT crt_; Outputs::CRT::CRT crt_;
uint16_t palette_[32]{};
}; };
} }