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https://github.com/TomHarte/CLK.git
synced 2026-04-20 10:17:05 +00:00
Completes test cases.
This commit is contained in:
Thomas Harte
@@ -20,6 +20,203 @@ template <Model model, bool validate_reserved_bits, Operation operation> Instruc
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// Otherwise, validation depends on operation
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// (and, in principle, processor model).
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switch(operation) {
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case Operation::addmex: case Operation::addzex:
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case Operation::bcctrx: case Operation::bclrx:
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case Operation::cntlzdx: case Operation::cntlzwx:
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case Operation::extsbx: case Operation::extshx: case Operation::extswx:
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case Operation::fmulx: case Operation::fmulsx:
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case Operation::negx:
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case Operation::subfmex: case Operation::subfzex:
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if(opcode & 0b000000'00000'00000'11111'0000000000'0) return Instruction(opcode);
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break;
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case Operation::cmp: case Operation::cmpl:
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if(opcode & 0b000000'00010'00000'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::cmpi: case Operation::cmpli:
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if(opcode & 0b000000'00010'00000'00000'0000000000'0) return Instruction(opcode);
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break;
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case Operation::dcbf: case Operation::dcbi: case Operation::dcbst:
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case Operation::dcbt: case Operation::dcbtst: case Operation::dcbz:
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if(opcode & 0b000000'11111'00000'00000'0000000000'0) return Instruction(opcode);
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break;
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case Operation::crand: case Operation::crandc: case Operation::creqv:
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case Operation::crnand: case Operation::crnor: case Operation::cror:
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case Operation::crorc: case Operation::crxor:
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case Operation::eciwx: case Operation::ecowx:
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case Operation::lbzux: case Operation::lbzx:
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case Operation::ldarx:
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case Operation::ldux: case Operation::ldx:
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case Operation::lfdux: case Operation::lfdx:
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case Operation::lfsux: case Operation::lfsx:
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case Operation::lhaux: case Operation::lhax: case Operation::lhbrx:
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case Operation::lhzux: case Operation::lhzx:
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case Operation::lswi: case Operation::lswx:
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case Operation::lwarx: case Operation::lwaux: case Operation::lwax: case Operation::lwbrx:
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case Operation::lwzux: case Operation::lwzx:
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case Operation::mfspr: case Operation::mftb:
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case Operation::mtspr:
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case Operation::stbux: case Operation::stbx:
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case Operation::stdux: case Operation::stdx:
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case Operation::stfdux: case Operation::stfdx:
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case Operation::stfiwx:
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case Operation::stfsux: case Operation::stfsx:
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case Operation::sthbrx:
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case Operation::sthux: case Operation::sthx:
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case Operation::stswi: case Operation::stswx:
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case Operation::stwbrx:
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case Operation::stwux: case Operation::stwx:
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case Operation::td: case Operation::tw:
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if(opcode & 0b000000'00000'00000'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::fabsx: case Operation::fcfidx:
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case Operation::fctidx: case Operation::fctidzx:
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case Operation::fctiwx: case Operation::fctiwzx:
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case Operation::fmrx: case Operation::fnabsx:
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case Operation::fnegx: case Operation::frspx:
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if(opcode & 0b000000'00000'11111'00000'0000000000'0) return Instruction(opcode);
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break;
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case Operation::faddx: case Operation::faddsx:
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case Operation::fdivx: case Operation::fdivsx:
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case Operation::fsubx: case Operation::fsubsx:
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if(opcode & 0b000000'00000'00000'00000'1111100000'0) return Instruction(opcode);
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break;
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case Operation::fcmpo: case Operation::fcmpu:
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if(opcode & 0b000000'00011'00000'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::fresx: case Operation::frsqrtex:
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case Operation::fsqrtx: case Operation::fsqrtsx:
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if(opcode & 0b000000'00000'11111'00000'1111100000'1) return Instruction(opcode);
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break;
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case Operation::icbi:
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if(opcode & 0b000000'11111'00000'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::eieio:
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case Operation::isync:
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case Operation::rfi:
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case Operation::slbia:
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case Operation::sync:
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case Operation::tlbia:
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case Operation::tlbsync:
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if(opcode & 0b000000'11111'11111'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mcrf: case Operation::mcrfs:
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if(opcode & 0b000000'00011'00011'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mcrxr:
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if(opcode & 0b000000'00011'11111'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mfcr:
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case Operation::mfmsr:
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case Operation::mtmsr:
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if(opcode & 0b000000'00000'11111'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mffsx:
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case Operation::mtfsb0x:
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case Operation::mtfsb1x:
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if(opcode & 0b000000'00000'11111'11111'0000000000'0) return Instruction(opcode);
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break;
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case Operation::mtfsfx:
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if(opcode & 0b000000'10000'00001'00000'0000000000'0) return Instruction(opcode);
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break;
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case Operation::mtfsfix:
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if(opcode & 0b000000'00011'11111'00001'0000000000'0) return Instruction(opcode);
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break;
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case Operation::mtsr:
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if(opcode & 0b000000'00000'10000'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mtsrin:
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if(opcode & 0b000000'00000'11111'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::mulhdx: case Operation::mulhdux:
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case Operation::mulhwx: case Operation::mulhwux:
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if(opcode & 0b000000'00000'00000'00000'1000000000'0) return Instruction(opcode);
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break;
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case Operation::sc:
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if(opcode & 0b000000'11111'11111'11111'1111111110'1) return Instruction(opcode);
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break;
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case Operation::slbie:
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case Operation::tlbie:
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if(opcode & 0b000000'11111'11111'00000'0000000000'1) return Instruction(opcode);
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break;
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case Operation::stwcx_:
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if(!(opcode & 0b000000'00000'00000'00000'0000000000'1)) return Instruction(opcode);
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break;
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case Operation::clcs:
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if(opcode & 0b000000'00000'00000'11111'0000000000'1) return Instruction(opcode);
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break;
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case Operation::addx: case Operation::addcx: case Operation::addex:
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case Operation::addi: case Operation::addic: case Operation::addic_:
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case Operation::addis:
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case Operation::andx: case Operation::andcx:
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case Operation::andi_: case Operation::andis_:
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case Operation::bx: case Operation::bcx:
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case Operation::divdx: case Operation::divdux:
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case Operation::divwx: case Operation::divwux:
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case Operation::eqvx:
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case Operation::fmaddx: case Operation::fmaddsx:
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case Operation::fmsubx: case Operation::fmsubsx:
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case Operation::fnmaddx: case Operation::fnmaddsx:
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case Operation::fnmsubx: case Operation::fnmsubsx:
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case Operation::fselx:
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case Operation::lbz: case Operation::lbzu:
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case Operation::lfd: case Operation::lfdu:
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case Operation::lfs: case Operation::lfsu:
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case Operation::lha: case Operation::lhau:
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case Operation::lhz: case Operation::lhzu:
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case Operation::lmw: case Operation::lwa:
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case Operation::lwz: case Operation::lwzu:
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case Operation::mulld: case Operation::mulli: case Operation::mullwx:
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case Operation::nandx: case Operation::norx:
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case Operation::orx: case Operation::orcx:
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case Operation::ori: case Operation::oris:
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case Operation::rlwimix: case Operation::rlwinmx: case Operation::rlwnmx:
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case Operation::sldx: case Operation::slwx:
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case Operation::sradx: case Operation::sradix:
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case Operation::srawx: case Operation::srawix:
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case Operation::srdx: case Operation::srwx:
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case Operation::stb: case Operation::stbu:
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case Operation::std: case Operation::stdcx_: case Operation::stdu:
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case Operation::stfd: case Operation::stfdu:
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case Operation::stfs: case Operation::stfsu:
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case Operation::sth: case Operation::sthu:
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case Operation::stmw:
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case Operation::stw: case Operation::stwu:
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case Operation::subfx: case Operation::subfcx: case Operation::subfex:
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case Operation::subfic:
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case Operation::tdi: case Operation::twi:
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case Operation::xorx: case Operation::xori: case Operation::xoris:
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// TODO: ld ldu
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// TODO: rldclx rldcrx rldicx rldicrx rldimix
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break;
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}
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return Instruction(operation, opcode, is_supervisor);
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}
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@@ -338,7 +535,7 @@ Instruction Decoder<model, validate_reserved_bits>::decode(uint32_t opcode) {
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return Instruction(opcode);
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}
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// std and stdu
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// std and stdu [TODO: or ld and ldu?]
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switch(opcode & 0b111111'00'00000000'00000000'000000'11) {
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case 0b111110'00'00000000'00000000'000000'00: return instruction<model, validate_reserved_bits, Operation::std>(opcode);
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case 0b111110'00'00000000'00000000'000000'01:
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