diff --git a/InstructionSets/6809/OperationMapper.hpp b/InstructionSets/6809/OperationMapper.hpp index 457a8bcfe..1aba58554 100644 --- a/InstructionSets/6809/OperationMapper.hpp +++ b/InstructionSets/6809/OperationMapper.hpp @@ -8,6 +8,8 @@ #pragma once +#include + // Cf. https://techheap.packetizer.com/processors/6809/6809Instructions.html // // Subject to corrections: diff --git a/OSBindings/Mac/Clock SignalTests/6809OperationMapperTests.mm b/OSBindings/Mac/Clock SignalTests/6809OperationMapperTests.mm index 0237017c5..5b0cdbf2a 100644 --- a/OSBindings/Mac/Clock SignalTests/6809OperationMapperTests.mm +++ b/OSBindings/Mac/Clock SignalTests/6809OperationMapperTests.mm @@ -12,6 +12,8 @@ #include "Dispatcher.hpp" #include "InstructionSets/6809/OperationMapper.hpp" +#include + using namespace InstructionSet::M6809; namespace { @@ -29,6 +31,38 @@ template std::pair capture(const uint8_t @implementation M6809OperationMapperTests +- (void)testOpcodeLengths { + const std::unordered_map lengths = { + {0x00, 2}, {0x01, 1}, {0x02, 1}, {0x03, 2}, {0x04, 2}, {0x05, 1}, {0x06, 2}, {0x07, 2}, + {0x08, 2}, {0x09, 2}, {0x0a, 2}, {0x0b, 1}, {0x0c, 2}, {0x0d, 2}, {0x0e, 2}, {0x0f, 2}, + }; + + for(const auto &pair : lengths) { + const auto decoded = [&] { + switch(pair.first >> 8) { + default: return capture(pair.first & 0xff); + } + } (); + + const auto expected_length = [&] { + switch(decoded.second) { + case AddressingMode::Direct: return 2; + case AddressingMode::Extended: return 3; + case AddressingMode::Illegal: return 1; + case AddressingMode::Inherent: return 1; + case AddressingMode::Relative8: return 2; + case AddressingMode::Relative16: return 3; + case AddressingMode::Immediate8: return 2; + case AddressingMode::Immediate16: return 3; + case AddressingMode::Variant: return 1; + default: __builtin_unreachable(); + } + } () + bool(pair.first >> 8); + + XCTAssertEqual(expected_length, pair.second); + } +}; + - (void) testOpcode:(uint8_t)opcode page:(Page)page @@ -52,22 +86,22 @@ template std::pair capture(const uint8_t [self testOpcode:0xd9 page:Page::Page0 isOperation:Operation::ADCB addressingMode:AddressingMode::Direct]; [self testOpcode:0xab page:Page::Page0 isOperation:Operation::ADDA addressingMode:AddressingMode::Indexed]; [self testOpcode:0xf3 page:Page::Page0 isOperation:Operation::ADDD addressingMode:AddressingMode::Extended]; - [self testOpcode:0xc4 page:Page::Page0 isOperation:Operation::ANDB addressingMode:AddressingMode::Immediate]; - [self testOpcode:0x1c page:Page::Page0 isOperation:Operation::ANDCC addressingMode:AddressingMode::Immediate]; + [self testOpcode:0xc4 page:Page::Page0 isOperation:Operation::ANDB addressingMode:AddressingMode::Immediate8]; + [self testOpcode:0x1c page:Page::Page0 isOperation:Operation::ANDCC addressingMode:AddressingMode::Immediate8]; [self testOpcode:0x08 page:Page::Page0 isOperation:Operation::LSL addressingMode:AddressingMode::Direct]; [self testOpcode:0x57 page:Page::Page0 isOperation:Operation::ASRB addressingMode:AddressingMode::Inherent]; - [self testOpcode:0x24 page:Page::Page0 isOperation:Operation::BCC addressingMode:AddressingMode::Relative]; + [self testOpcode:0x24 page:Page::Page0 isOperation:Operation::BCC addressingMode:AddressingMode::Relative8]; [self testOpcode:0xa5 page:Page::Page0 isOperation:Operation::BITA addressingMode:AddressingMode::Indexed]; - [self testOpcode:0x20 page:Page::Page0 isOperation:Operation::BRA addressingMode:AddressingMode::Relative]; - [self testOpcode:0x8d page:Page::Page0 isOperation:Operation::BSR addressingMode:AddressingMode::Relative]; + [self testOpcode:0x20 page:Page::Page0 isOperation:Operation::BRA addressingMode:AddressingMode::Relative8]; + [self testOpcode:0x8d page:Page::Page0 isOperation:Operation::BSR addressingMode:AddressingMode::Relative8]; [self testOpcode:0x5f page:Page::Page0 isOperation:Operation::CLRB addressingMode:AddressingMode::Inherent]; [self testOpcode:0x7f page:Page::Page0 isOperation:Operation::CLR addressingMode:AddressingMode::Extended]; - [self testOpcode:0x81 page:Page::Page0 isOperation:Operation::CMPA addressingMode:AddressingMode::Immediate]; + [self testOpcode:0x81 page:Page::Page0 isOperation:Operation::CMPA addressingMode:AddressingMode::Immediate8]; [self testOpcode:0xa3 page:Page::Page1 isOperation:Operation::CMPD addressingMode:AddressingMode::Indexed]; [self testOpcode:0xa3 page:Page::Page2 isOperation:Operation::CMPU addressingMode:AddressingMode::Indexed]; [self testOpcode:0x53 page:Page::Page0 isOperation:Operation::COMB addressingMode:AddressingMode::Inherent]; [self testOpcode:0x73 page:Page::Page0 isOperation:Operation::COM addressingMode:AddressingMode::Extended]; - [self testOpcode:0x3c page:Page::Page0 isOperation:Operation::CWAI addressingMode:AddressingMode::Immediate]; + [self testOpcode:0x3c page:Page::Page0 isOperation:Operation::CWAI addressingMode:AddressingMode::Immediate8]; [self testOpcode:0x19 page:Page::Page0 isOperation:Operation::DAA addressingMode:AddressingMode::Inherent]; [self testOpcode:0x4a page:Page::Page0 isOperation:Operation::DECA addressingMode:AddressingMode::Inherent]; [self testOpcode:0x0a page:Page::Page0 isOperation:Operation::DEC addressingMode:AddressingMode::Direct]; @@ -77,26 +111,26 @@ template std::pair capture(const uint8_t [self testOpcode:0x0c page:Page::Page0 isOperation:Operation::INC addressingMode:AddressingMode::Direct]; [self testOpcode:0x6e page:Page::Page0 isOperation:Operation::JMP addressingMode:AddressingMode::Indexed]; [self testOpcode:0x9d page:Page::Page0 isOperation:Operation::JSR addressingMode:AddressingMode::Direct]; - [self testOpcode:0x24 page:Page::Page1 isOperation:Operation::LBCC addressingMode:AddressingMode::Relative]; + [self testOpcode:0x24 page:Page::Page1 isOperation:Operation::LBCC addressingMode:AddressingMode::Relative16]; [self testOpcode:0xe6 page:Page::Page0 isOperation:Operation::LDB addressingMode:AddressingMode::Indexed]; - [self testOpcode:0x8e page:Page::Page1 isOperation:Operation::LDY addressingMode:AddressingMode::Immediate]; + [self testOpcode:0x8e page:Page::Page1 isOperation:Operation::LDY addressingMode:AddressingMode::Immediate16]; [self testOpcode:0x32 page:Page::Page0 isOperation:Operation::LEAS addressingMode:AddressingMode::Indexed]; [self testOpcode:0x74 page:Page::Page0 isOperation:Operation::LSR addressingMode:AddressingMode::Extended]; [self testOpcode:0x3d page:Page::Page0 isOperation:Operation::MUL addressingMode:AddressingMode::Inherent]; [self testOpcode:0x40 page:Page::Page0 isOperation:Operation::NEGA addressingMode:AddressingMode::Inherent]; [self testOpcode:0x00 page:Page::Page0 isOperation:Operation::NEG addressingMode:AddressingMode::Direct]; [self testOpcode:0x12 page:Page::Page0 isOperation:Operation::NOP addressingMode:AddressingMode::Inherent]; - [self testOpcode:0x8a page:Page::Page0 isOperation:Operation::ORA addressingMode:AddressingMode::Immediate]; - [self testOpcode:0x1a page:Page::Page0 isOperation:Operation::ORCC addressingMode:AddressingMode::Immediate]; - [self testOpcode:0x34 page:Page::Page0 isOperation:Operation::PSHS addressingMode:AddressingMode::Immediate]; - [self testOpcode:0x36 page:Page::Page0 isOperation:Operation::PSHU addressingMode:AddressingMode::Immediate]; - [self testOpcode:0x37 page:Page::Page0 isOperation:Operation::PULU addressingMode:AddressingMode::Immediate]; + [self testOpcode:0x8a page:Page::Page0 isOperation:Operation::ORA addressingMode:AddressingMode::Immediate8]; + [self testOpcode:0x1a page:Page::Page0 isOperation:Operation::ORCC addressingMode:AddressingMode::Immediate8]; + [self testOpcode:0x34 page:Page::Page0 isOperation:Operation::PSHS addressingMode:AddressingMode::Immediate8]; + [self testOpcode:0x36 page:Page::Page0 isOperation:Operation::PSHU addressingMode:AddressingMode::Immediate8]; + [self testOpcode:0x37 page:Page::Page0 isOperation:Operation::PULU addressingMode:AddressingMode::Immediate8]; [self testOpcode:0x59 page:Page::Page0 isOperation:Operation::ROLB addressingMode:AddressingMode::Inherent]; [self testOpcode:0x69 page:Page::Page0 isOperation:Operation::ROL addressingMode:AddressingMode::Indexed]; [self testOpcode:0x76 page:Page::Page0 isOperation:Operation::ROR addressingMode:AddressingMode::Extended]; [self testOpcode:0x3b page:Page::Page0 isOperation:Operation::RTI addressingMode:AddressingMode::Inherent]; [self testOpcode:0x39 page:Page::Page0 isOperation:Operation::RTS addressingMode:AddressingMode::Inherent]; - [self testOpcode:0xc2 page:Page::Page0 isOperation:Operation::SBCB addressingMode:AddressingMode::Immediate]; + [self testOpcode:0xc2 page:Page::Page0 isOperation:Operation::SBCB addressingMode:AddressingMode::Immediate8]; [self testOpcode:0x1d page:Page::Page0 isOperation:Operation::SEX addressingMode:AddressingMode::Inherent]; [self testOpcode:0xe7 page:Page::Page0 isOperation:Operation::STB addressingMode:AddressingMode::Indexed]; [self testOpcode:0xbf page:Page::Page1 isOperation:Operation::STY addressingMode:AddressingMode::Extended]; diff --git a/OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm b/OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm index 0fe69c525..a5d4fd36d 100644 --- a/OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm +++ b/OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm @@ -141,7 +141,7 @@ struct CapturingZ80: public CPU::Z80::BusHandler { break; case CPU::Z80::PartialMachineCycle::Internal: - for(int c = 0; c < cycle.length.cycles().as(); c++) { + for(int c = 0; c < cycle.length.reduce().as(); c++) { contentions_48k_.emplace_back(); contentions_48k_.back().address = *cycle.address; contentions_48k_.back().length = 1;