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Adds signalling of DACK.

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This commit is contained in:
Thomas Harte 2019-09-14 13:48:33 -04:00
parent c849188016
commit 243e40cd79
3 changed files with 15 additions and 8 deletions
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5
Components/5380/ncr5380.cpp
View File

@ -20,7 +20,7 @@ NCR5380::NCR5380(SCSI::Bus &bus, int clock_rate) :
device_id_ = bus_.add_device();
}
void NCR5380::write(int address, uint8_t value) {
void NCR5380::write(int address, uint8_t value, bool dma_acknowledge) {
switch(address & 7) {
case 0:
LOG("[SCSI 0] Set current SCSI bus state to " << PADHEX(2) << int(value));
@ -116,7 +116,7 @@ void NCR5380::write(int address, uint8_t value) {
}
}
uint8_t NCR5380::read(int address) {
uint8_t NCR5380::read(int address, bool dma_acknowledge) {
switch(address & 7) {
case 0:
LOG("[SCSI 0] Get current SCSI bus state: " << PADHEX(2) << (bus_.get_state() & 0xff));
@ -302,6 +302,7 @@ void NCR5380::run_for(Cycles cycles) {
void NCR5380::set_execution_state(ExecutionState state) {
time_in_state_ = 0;
state_ = state;
if(state != ExecutionState::PerformingDMA) dma_operation_ = DMAOperation::Ready;
update_clocking_observer();
}

9
Components/5380/ncr5380.hpp
View File

@ -27,10 +27,10 @@ class NCR5380 final: public ClockingHint::Source {
NCR5380(SCSI::Bus &bus, int clock_rate);
/*! Writes @c value to @c address. */
void write(int address, uint8_t value);
void write(int address, uint8_t value, bool dma_acknowledge = false);
/*! Reads from @c address. */
uint8_t read(int address);
uint8_t read(int address, bool dma_acknowledge = false);
/*!
As per its design manual:
@ -74,6 +74,11 @@ class NCR5380 final: public ClockingHint::Source {
WatchingBusy,
PerformingDMA,
} state_ = ExecutionState::None;
enum class DMAOperation {
Ready,
Reading,
Writing
} dma_operation_ = DMAOperation::Ready;
int time_in_state_ = 0;
bool lost_arbitration_ = false, arbitration_in_progress_ = false;

9
Machines/Apple/Macintosh/Macintosh.cpp
View File

@ -251,23 +251,24 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
case BusDevice::SCSI: {
const int register_address = word_address >> 3;
const bool dma_acknowledge = word_address & 0x100;
// Even accesses = read; odd = write.
if(*cycle.address & 1) {
// Odd access => this is a write. Data will be in the upper byte.
if(cycle.operation & Microcycle::Read) {
scsi_.write(register_address, 0xff);
scsi_.write(register_address, 0xff, dma_acknowledge);
} else {
if(cycle.operation & Microcycle::SelectWord) {
scsi_.write(register_address, cycle.value->halves.high);
scsi_.write(register_address, cycle.value->halves.high, dma_acknowledge);
} else {
scsi_.write(register_address, cycle.value->halves.low);
scsi_.write(register_address, cycle.value->halves.low, dma_acknowledge);
}
}
} else {
// Even access => this is a read.
if(cycle.operation & Microcycle::Read) {
const auto result = scsi_.read(register_address);
const auto result = scsi_.read(register_address, dma_acknowledge);
if(cycle.operation & Microcycle::SelectWord) {
// Data is loaded on the top part of the bus only.
cycle.value->full = uint16_t((result << 8) | 0xff);