1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-22 12:33:29 +00:00

Sets VPA for CIA accesses; logs a little more.

This commit is contained in:
Thomas Harte 2021-08-05 20:06:48 -04:00
parent b9f78f5d33
commit 25e2bd307a

View File

@ -95,8 +95,7 @@ class ConcreteMachine:
// Autovector interrupts. // Autovector interrupts.
if(cycle.operation & Microcycle::InterruptAcknowledge) { if(cycle.operation & Microcycle::InterruptAcknowledge) {
mc68000_.set_is_peripheral_address(true); mc68000_.set_is_peripheral_address(true);
} else { return HalfCycles(0);
mc68000_.set_is_peripheral_address(false);
} }
// Do nothing if no address is exposed. // Do nothing if no address is exposed.
@ -106,9 +105,9 @@ class ConcreteMachine:
// Grab the target address to pick a memory source. // Grab the target address to pick a memory source.
const uint32_t address = cycle.host_endian_byte_address(); const uint32_t address = cycle.host_endian_byte_address();
// if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord)) && !(cycle.operation & Microcycle::IsProgram)) {
// printf("%06x\n", *cycle.address); // Set VPA if this is [going to be] a CIA access.
// } mc68000_.set_is_peripheral_address((address & 0xe0'0000) == 0xa0'0000);
if(!memory_.regions[address >> 18].read_write_mask) { if(!memory_.regions[address >> 18].read_write_mask) {
if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) { if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) {
@ -345,6 +344,11 @@ class ConcreteMachine:
LOG("TODO: Stepping, etc; " << PADHEX(2) << +value); LOG("TODO: Stepping, etc; " << PADHEX(2) << +value);
} }
} }
uint8_t get_port_input(MOS::MOS6526::Port) {
LOG("Unexpected input for CIA B ");
return 0xff;
}
} cia_b_handler_; } cia_b_handler_;
HalfCycles cia_divider_; HalfCycles cia_divider_;