6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2026-04-22 08:16:42 +00:00
Code Issues Projects Releases Wiki Activity

Don't sign-extend ports (!).

Browse Source
This commit is contained in:
Thomas Harte
2023-11-16 11:17:12 -05:00
parent 233ec7b818
commit 25f0a373f3
3 changed files with 21 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
InstructionSets/x86/Decoder.cpp
+18 -7
View File
@@ -58,14 +58,16 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
#define RegAddr(op, dest, op_size, addr_size) \
SetOpSrcDestSize(op, DirectAddress, dest, op_size); \
displacement_size_ = addr_size; \
phase_ = Phase::DisplacementOrOperand
phase_ = Phase::DisplacementOrOperand; \
sign_extend_displacement_ = false
/// Handles instructions of the form jjkk, Ax where the former is implicitly an address.
#define AddrReg(op, source, op_size, addr_size) \
SetOpSrcDestSize(op, source, DirectAddress, op_size); \
displacement_size_ = addr_size; \
destination_ = Source::DirectAddress; \
phase_ = Phase::DisplacementOrOperand
phase_ = Phase::DisplacementOrOperand; \
sign_extend_displacement_ = false
/// Covers both `mem/reg, reg` and `reg, mem/reg`.
#define MemRegReg(op, format, size) \
@@ -1017,11 +1019,20 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
if(bytes_to_consume == outstanding_bytes) {
phase_ = Phase::ReadyToPost;
switch(displacement_size_) {
case DataSize::None: displacement_ = 0; break;
case DataSize::Byte: displacement_ = int8_t(inward_data_); break;
case DataSize::Word: displacement_ = int16_t(inward_data_); break;
case DataSize::DWord: displacement_ = int32_t(inward_data_); break;
if(!sign_extend_displacement_) {
switch(displacement_size_) {
case DataSize::None: displacement_ = 0; break;
case DataSize::Byte: displacement_ = uint8_t(inward_data_); break;
case DataSize::Word: displacement_ = uint16_t(inward_data_); break;
case DataSize::DWord: displacement_ = int32_t(inward_data_); break;
}
} else {
switch(displacement_size_) {
case DataSize::None: displacement_ = 0; break;
case DataSize::Byte: displacement_ = int8_t(inward_data_); break;
case DataSize::Word: displacement_ = int16_t(inward_data_); break;
case DataSize::DWord: displacement_ = int32_t(inward_data_); break;
}
}
inward_data_ >>= bit_size(displacement_size_);