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Fix data aborts.
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c485097eed
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265d151879
@ -551,7 +551,7 @@ class ConcreteMachine:
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uint32_t instruction;
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uint32_t instruction;
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const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode(), false);
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const bool did_read = executor_.bus.read(pc, instruction, executor_.registers().mode(), false);
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return pipeline_.exchange(
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return pipeline_.exchange(
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instruction,
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did_read ? instruction : Pipeline::SWI,
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did_read ? Pipeline::SWISubversion::None : Pipeline::SWISubversion::DataAbort);
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did_read ? Pipeline::SWISubversion::None : Pipeline::SWISubversion::DataAbort);
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}
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}
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@ -563,6 +563,8 @@ class ConcreteMachine:
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FIQ,
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FIQ,
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};
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};
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static constexpr uint32_t SWI = 0xef'000000;
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uint32_t exchange(uint32_t next, SWISubversion subversion) {
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uint32_t exchange(uint32_t next, SWISubversion subversion) {
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const uint32_t result = upcoming_[active_].opcode;
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const uint32_t result = upcoming_[active_].opcode;
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latched_subversion_ = upcoming_[active_].subversion;
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latched_subversion_ = upcoming_[active_].subversion;
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@ -586,7 +588,7 @@ class ConcreteMachine:
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// In practice I got into a bit of a race condition between interrupt scheduling and
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// In practice I got into a bit of a race condition between interrupt scheduling and
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// flags changes, so have backed off for now.
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// flags changes, so have backed off for now.
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void reschedule(SWISubversion subversion) {
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void reschedule(SWISubversion subversion) {
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upcoming_[active_].opcode = 0xef'000000;
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upcoming_[active_].opcode = SWI;
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upcoming_[active_].subversion = subversion;
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upcoming_[active_].subversion = subversion;
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}
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}
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